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[Qemu-devel] [PATCH v4 26/64] disas/ppc: Handle popcnt and cnttz
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 26/64] disas/ppc: Handle popcnt and cnttz |
Date: |
Wed, 23 Nov 2016 14:01:23 +0100 |
Signed-off-by: Richard Henderson <address@hidden>
---
disas/ppc.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/disas/ppc.c b/disas/ppc.c
index bd05623..ed7e0d0 100644
--- a/disas/ppc.c
+++ b/disas/ppc.c
@@ -1955,6 +1955,9 @@ extract_tbr (unsigned long insn,
#define POWER4 PPC_OPCODE_POWER4
#define POWER5 PPC_OPCODE_POWER5
#define POWER6 PPC_OPCODE_POWER6
+/* Documentation purposes only; we don't actually check the isa for disas. */
+#define POWER7 PPC_OPCODE_POWER6
+#define POWER9 PPC_OPCODE_POWER6
#define CELL PPC_OPCODE_CELL
#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
@@ -3589,6 +3592,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB }
},
{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
+{ "popcntw", X(31,378), XRB_MASK, POWER7, { RA, RS } },
+{ "popcntd", X(31,506), XRB_MASK, POWER7, { RA, RS } },
+
+{ "cnttzw", XRC(31,538,0), XRB_MASK, POWER9, { RA, RS } },
+{ "cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, { RA, RS } },
+{ "cnttzd", XRC(31,570,0), XRB_MASK, POWER9, { RA, RS } },
+{ "cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, { RA, RS } },
{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
--
2.7.4
- [Qemu-devel] [PATCH v4 16/64] target-mips: Use the new extract op, (continued)
- [Qemu-devel] [PATCH v4 16/64] target-mips: Use the new extract op, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 15/64] target-i386: Use new deposit and extract ops, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 17/64] target-ppc: Use the new deposit and extract ops, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 19/64] tcg/optimize: Fold movcond 0/1 into setcond, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 18/64] target-s390x: Use the new deposit and extract ops, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 20/64] tcg: Add markup for output requires new register, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 22/64] tcg: Pass the opcode width to target_parse_constraint, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 21/64] tcg: Transition flat op_defs array to a target callback, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 25/64] disas/i386.c: Handle tzcnt, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 23/64] tcg: Allow an operand to be matching or a constant, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 26/64] disas/ppc: Handle popcnt and cnttz,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 24/64] tcg: Add clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 27/64] target-alpha: Use the ctz and clz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 29/64] target-microblaze: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 28/64] target-cris: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 31/64] target-openrisc: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 30/64] target-mips: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 32/64] target-ppc: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 33/64] target-s390x: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 34/64] target-tilegx: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 36/64] target-unicore32: Use clz opcode, Richard Henderson, 2016/11/23