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[Qemu-devel] [PULL 06/12] hw/arm/virt: Declare virtio-mmio as dma cache
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/12] hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI |
Date: |
Fri, 10 Feb 2017 18:07:56 +0000 |
From: Alexander Graf <address@hidden>
Virtio-mmio devices can directly access guest memory and do so in cache
coherent fashion. Tell the guest about that fact when it's using ACPI.
Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Ard Biesheuvel <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/virt-acpi-build.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 07a10ac..8955a9d 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -135,6 +135,7 @@ static void acpi_dsdt_add_virtio(Aml *scope,
Aml *dev = aml_device("VR%02u", i);
aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
Aml *crs = aml_resource_template();
aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
--
2.7.4
- [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 03/12] target-arm: Add support for PMU register PMINTENSET_EL1, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 05/12] target-arm: Declare virtio-mmio as dma-coherent in dt, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 04/12] target-arm: Enable vPMU support under TCG mode, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 06/12] hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI,
Peter Maydell <=
- [Qemu-devel] [PULL 07/12] hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 09/12] aspeed: check for negative values returned by blk_getlength(), Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 02/12] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 12/12] aspeed/smc: use a modulo to check segment limits, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 11/12] aspeed/smc: handle dummies only in fast read mode, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 10/12] aspeed: remove useless comment on controller segment size, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 08/12] hw/arm/virt: Declare fwcfg as dma cache coherent in dt, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 01/12] target-arm: Add support for PMU register PMSELR_EL0, Peter Maydell, 2017/02/10
- Re: [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2017/02/13