Re: [Qemu-devel] [PATCH v2 03/29] target/s390x: implement local-TLB-clearing in IPTE

[Aurelien Jarno]

On 2017-05-30 11:01, Thomas Huth wrote:
> On 29.05.2017 21:24, Aurelien Jarno wrote:
> > And at the same time make IPTE SMP aware.
> > 
> > Signed-off-by: Aurelien Jarno <address@hidden>
> > ---
> >  target/s390x/helper.h     |  2 +-
> >  target/s390x/mem_helper.c | 19 ++++++++++++-------
> >  target/s390x/translate.c  |  6 +++++-
> >  3 files changed, 18 insertions(+), 9 deletions(-)
> [...]
> > @@ -1092,13 +1091,19 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, 
> > uint64_t vaddr)
> >  
> >      /* XXX we exploit the fact that Linux passes the exact virtual
> >         address here - it's not obliged to! */
> > -    tlb_flush_page(cs, page);
> > +    /* XXX: the LC bit should be considered as 0 if the local-TLB-clearing
> > +       facility is not installed.  */
> 
> That should be easy, I think:
> 
>     if (!s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
>         m4 = 0;
>     }

I agree, it should be easy to implement. The reason I haven't implemented
it is that we currently don't have a good model for the TCG CPU, so we
don't have a way to easily enable it or not (though that is changing a
bit with your later patches). In practice we expose supported features
through STFL/SFTLE, but we don't do any check to see if the features or
instructions are enable or not.

In addition this feature is not fully implemented, it should also be
done for the IDTE instruction, which we don't implement (i have a local
patch for that, but not yet ready).

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
address@hidden                 http://www.aurel32.net