Re: [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG

[David Hildenbrand]

On 03.07.2017 13:07, Thomas Huth wrote:
> On 30.06.2017 21:22, Richard Henderson wrote:
>> On 06/29/2017 12:05 AM, Thomas Huth wrote:
>>> However, I'm not sure whether you can simply ignore the clearing-by-ASCE
>>> stuff in this case. For example, according to the PoP:
>>>
>>> "When the clearing-by-ASCE-option bit (bit 52 of gen-
>>>   eral register R2 is one), the M4 field is ignored."
>>>
>>> And the idte helper function currently always takes the M4 field into
>>> account...
>>
>> I don't see that quote.
> 
> Which version of the Principles of Operation are you using? I just
> checked, and that sentence seems to be available in version SA22-7832-10
> (but it is not in SA22-7832-09 yet).
> 
>  Thomas
> 
> 

I think that part of the PoP is quite confusing.


"When the local-TLB-clearing facility is not installed [...]
the term “__specified__ CPU or CPUs” means all of the CPUs in the
configuration."

"When the local-TLB-clearing facility is installed [...]
the term “__specified__ CPU or CPUs” means only the CPU
executing the IDTE instruction (the local CPU)."

"When the clearing-by-ASCE-option bit, bit 52 of gen-
eral register R2, is zero [...] in the
__specified__ CPU or CPUs in the configuration are
cleared of (1) all TLB table entries of the designated [...]"

"When the clearing-by-ASCE-option bit is one [...]
but it does clear, from the TLBs in __all__ CPUs in the [...]"


So one could assume, that local-tlb-clearing does not apply to
clearing-by-ASCE-option. However:

"When bit 52 of general register R2, the clearing-by-
ASCE-option bit, is one, the clearing-by-ASCE oper-
ation is specified. [...] The TLBs of the __specified__ CPU or CPUs in
the configuration [...]"


But:

"When the clearing-by-ASCE-option bit (bit 52 of gen-
eral register R2 is one), the M4 field is ignored."

However also "Common Operation" section rather reads like
local-TLB-clearing applies to any mode.

Also the description of local-TLB-clearing is quite general:

"Local-TLB-Clearing Facility
The local-TLB-clearing facility may be available on a
model implementing z/Architecture. The facility may
provide performance improvements for the INVALI-
DATE DAT TABLE ENTRY and INVALIDATE PAGE
TABLE ENTRY instructions by allowing the program
to specify whether TLB clearing should be done in all
CPUs of the configuration or only in the CPU execut-
ing the instruction."


My interpretation:

local-TLB-clearing was introduced after IDTES but before EDAT2 (M4 bit
2). I think "m4 is ignored" should rather mean "M4 bit 2 is ignored".
Especially as this sentence was added later, I assume it is connected to
EDAT2, not local-TLB-clearing.


For now (!SMP) it should really matter. Opinions?


-- 

Thanks,

David