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[Qemu-devel] [PATCH v2 21/27] target/sh4: Tidy misc illegal insn checks
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 21/27] target/sh4: Tidy misc illegal insn checks |
Date: |
Thu, 6 Jul 2017 16:21:05 -1000 |
Now that we have a do_illegal label, use goto in order
to self-document the forcing of the exception.
Signed-off-by: Richard Henderson <address@hidden>
---
target/sh4/translate.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index a4370c6..06cf649 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1079,8 +1079,9 @@ static void _decode_opc(DisasContext * ctx)
if (ctx->tbflags & FPSCR_PR) {
TCGv_i64 fp0, fp1;
- if (ctx->opcode & 0x0110)
- break; /* illegal instruction */
+ if (ctx->opcode & 0x0110) {
+ goto do_illegal;
+ }
fp0 = tcg_temp_new_i64();
fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, B11_8);
@@ -1142,7 +1143,7 @@ static void _decode_opc(DisasContext * ctx)
{
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_PR) {
- break; /* illegal instruction */
+ goto do_illegal;
} else {
gen_helper_fmac_FT(FREG(B11_8), cpu_env,
FREG(0), FREG(B7_4), FREG(B11_8));
@@ -1693,8 +1694,9 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_PR) {
TCGv_i64 fp;
- if (ctx->opcode & 0x0100)
- break; /* illegal instruction */
+ if (ctx->opcode & 0x0100) {
+ goto do_illegal;
+ }
fp = tcg_temp_new_i64();
gen_helper_float_DT(fp, cpu_env, cpu_fpul);
gen_store_fpr64(ctx, fp, B11_8);
@@ -1708,8 +1710,9 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_PR) {
TCGv_i64 fp;
- if (ctx->opcode & 0x0100)
- break; /* illegal instruction */
+ if (ctx->opcode & 0x0100) {
+ goto do_illegal;
+ }
fp = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp, B11_8);
gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp);
@@ -1730,8 +1733,9 @@ static void _decode_opc(DisasContext * ctx)
case 0xf06d: /* fsqrt FRn */
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_PR) {
- if (ctx->opcode & 0x0100)
- break; /* illegal instruction */
+ if (ctx->opcode & 0x0100) {
+ goto do_illegal;
+ }
TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp, B11_8);
gen_helper_fsqrt_DT(fp, cpu_env, fp);
--
2.9.4
- Re: [Qemu-devel] [PATCH v2 17/27] target/sh4: Simplify 64-bit fp reg-reg move, (continued)
- [Qemu-devel] [PATCH v2 18/27] target/sh4: Unify code for CHECK_NOT_DELAY_SLOT, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 19/27] target/sh4: Unify code for CHECK_PRIVILEGED, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 20/27] target/sh4: Unify code for CHECK_FPU_ENABLED, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 21/27] target/sh4: Tidy misc illegal insn checks,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 22/27] target/sh4: Introduce CHECK_FPSCR_PR_*, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 24/27] target/sh4: Implement fpchg, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 23/27] target/sh4: Introduce CHECK_SH4A, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 25/27] target/sh4: Add missing FPSCR.PR == 0 checks, Richard Henderson, 2017/07/06