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[Qemu-devel] [PATCH 11/16] target/xtensa: drop DisasContext::litbase
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 11/16] target/xtensa: drop DisasContext::litbase |
Date: |
Fri, 3 Nov 2017 20:45:16 -0700 |
It doesn't help much, always-set bit 0 of the LITBASE SR is easy to
compensate with decrement of the l32r immediate argument.
Signed-off-by: Max Filippov <address@hidden>
---
target/xtensa/translate.c | 27 +++++----------------------
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 0460edf61389..fb6a4c979590 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -59,7 +59,6 @@ typedef struct DisasContext {
int ring;
uint32_t lbeg;
uint32_t lend;
- TCGv_i32 litbase;
int is_jmp;
int singlestep_enabled;
@@ -266,21 +265,6 @@ static inline bool option_enabled(DisasContext *dc, int
opt)
return xtensa_option_enabled(dc->config, opt);
}
-static void init_litbase(DisasContext *dc)
-{
- if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
- dc->litbase = tcg_temp_local_new_i32();
- tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
- }
-}
-
-static void reset_litbase(DisasContext *dc)
-{
- if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
- tcg_temp_free(dc->litbase);
- }
-}
-
static void init_sar_tracker(DisasContext *dc)
{
dc->sar_5bit = false;
@@ -1094,7 +1078,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock
*tb)
dc.slotbuf = xtensa_insnbuf_alloc(dc.config->isa);
}
- init_litbase(&dc);
init_sar_tracker(&dc);
if (dc.icount) {
dc.next_icount = tcg_temp_local_new_i32();
@@ -1169,7 +1152,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock
*tb)
dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
!tcg_op_buf_full());
done:
- reset_litbase(&dc);
reset_sar_tracker(&dc);
if (dc.icount) {
tcg_temp_free(dc.next_icount);
@@ -1672,12 +1654,13 @@ static void translate_l32r(DisasContext *dc, const
uint32_t arg[],
const uint32_t par[])
{
if (gen_window_check1(dc, arg[0])) {
- TCGv_i32 tmp = (dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
- tcg_const_i32(dc->raw_arg[1] - 1) :
- tcg_const_i32(arg[1]);
+ TCGv_i32 tmp;
if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
- tcg_gen_add_i32(tmp, tmp, dc->litbase);
+ tmp = tcg_const_i32(dc->raw_arg[1] - 1);
+ tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
+ } else {
+ tmp = tcg_const_i32(arg[1]);
}
tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring);
tcg_temp_free(tmp);
--
2.1.4
- [Qemu-devel] [PATCH 00/16] target/xtensa: switch to libisa, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 01/16] target/xtensa: pass actual frame size to the entry helper, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 05/16] target/xtensa: update import_core.sh script for libisa, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 04/16] target/xtensa: extract FPU2000 opcode translators, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 02/16] target/xtensa: import libisa source, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 03/16] target/xtensa: extract core opcode translators, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 10/16] target/xtensa: tests: fix memctl SR test, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 11/16] target/xtensa: drop DisasContext::litbase,
Max Filippov <=
- [Qemu-devel] [PATCH 13/16] target/xtensa: implement salt/saltu, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 09/16] target/xtensa: use libisa for instruction decoding, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 12/16] target/xtensa: add internal/noop SRs and opcodes, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 14/16] target/xtensa: implement GPIO32, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 15/16] target/xtensa: implement const16, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 16/16] target/xtensa: implement disassembler, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 08/16] target/xtensa: switch fsf to libisa, Max Filippov, 2017/11/03