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[Qemu-devel] [PATCH 15/16] target/xtensa: implement const16
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 15/16] target/xtensa: implement const16 |
Date: |
Fri, 3 Nov 2017 20:45:20 -0700 |
const16 is an opcode that shifts 16 lower bits of an address register
to the 16 upper bits and puts its immediate operand into the lower 16
bits. It is not controlled by an Xtensa option and doesn't have a fixed
opcode.
Signed-off-by: Max Filippov <address@hidden>
---
target/xtensa/translate.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index a84bbf3bedc3..f249e810d92c 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1526,6 +1526,17 @@ static void translate_clrb_expstate(DisasContext *dc,
const uint32_t arg[],
tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0]));
}
+static void translate_const16(DisasContext *dc, const uint32_t arg[],
+ const uint32_t par[])
+{
+ if (gen_window_check1(dc, arg[0])) {
+ TCGv_i32 v = tcg_temp_new_i32();
+
+ tcg_gen_shli_i32(v, cpu_R[arg[0]], 16);
+ tcg_gen_ori_i32(cpu_R[arg[0]], v, arg[1] & 0xffff);
+ }
+}
+
/* par[0]: privileged, par[1]: check memory access */
static void translate_dcache(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
@@ -2742,6 +2753,9 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "clrb_expstate",
.translate = translate_clrb_expstate,
}, {
+ .name = "const16",
+ .translate = translate_const16,
+ }, {
.name = "depbits",
.translate = translate_depbits,
}, {
--
2.1.4
- [Qemu-devel] [PATCH 05/16] target/xtensa: update import_core.sh script for libisa, (continued)
- [Qemu-devel] [PATCH 05/16] target/xtensa: update import_core.sh script for libisa, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 04/16] target/xtensa: extract FPU2000 opcode translators, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 02/16] target/xtensa: import libisa source, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 03/16] target/xtensa: extract core opcode translators, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 10/16] target/xtensa: tests: fix memctl SR test, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 11/16] target/xtensa: drop DisasContext::litbase, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 13/16] target/xtensa: implement salt/saltu, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 09/16] target/xtensa: use libisa for instruction decoding, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 12/16] target/xtensa: add internal/noop SRs and opcodes, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 14/16] target/xtensa: implement GPIO32, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 15/16] target/xtensa: implement const16,
Max Filippov <=
- [Qemu-devel] [PATCH 16/16] target/xtensa: implement disassembler, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 08/16] target/xtensa: switch fsf to libisa, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 06/16] target/xtensa: switch dc232b to libisa, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 07/16] target/xtensa: switch dc233c to libisa, Max Filippov, 2017/11/03
- Re: [Qemu-devel] [PATCH 00/16] target/xtensa: switch to libisa, no-reply, 2017/11/05
- Re: [Qemu-devel] [PATCH 00/16] target/xtensa: switch to libisa, no-reply, 2017/11/06