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Re: [Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers |
Date: |
Mon, 5 Feb 2018 05:55:49 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 |
On 02/04/2018 10:22 PM, Michael Clark wrote:
> Privileged control and status register helpers and page fault handling.
>
> Signed-off-by: Michael Clark <address@hidden>
> ---
> target/riscv/helper.c | 464 ++++++++++++++++++++++++++++++++++
> target/riscv/helper.h | 78 ++++++
> target/riscv/op_helper.c | 644
> +++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1186 insertions(+)
> create mode 100644 target/riscv/helper.c
> create mode 100644 target/riscv/helper.h
> create mode 100644 target/riscv/op_helper.c
Reviewed-by: Richard Henderson <address@hidden>
> +bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + if (interrupt_request & CPU_INTERRUPT_HARD) {
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> + int interruptno = riscv_cpu_hw_interrupts_pending(env);
> + if (interruptno + 1) {
Perhaps clearer as (interrupno >= 0) or (interruptno != -1).
But it's not actively wrong, so tidy at your convenience.
r~
- Re: [Qemu-devel] [PATCH v4 03/22] RISC-V CPU Core Definition, (continued)
[Qemu-devel] [PATCH v4 06/22] RISC-V FPU Support, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 07/22] RISC-V GDB Stub, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers, Michael Clark, 2018/02/05
- Re: [Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers,
Richard Henderson <=
[Qemu-devel] [PATCH v4 04/22] RISC-V Disassembler, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 09/22] RISC-V Physical Memory Protection, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 10/22] RISC-V Linux User Emulation, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 08/22] RISC-V TCG Code Generation, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 11/22] RISC-V HTIF Console, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 12/22] RISC-V HART Array, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 13/22] SiFive RISC-V CLINT Block, Michael Clark, 2018/02/05