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[Qemu-devel] [PULL 10/39] target/arm: Define init-svtor property for the
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/39] target/arm: Define init-svtor property for the reset secure VTOR value |
Date: |
Fri, 2 Mar 2018 11:06:11 +0000 |
The Cortex-M33 allows the system to specify the reset value of the
secure Vector Table Offset Register (VTOR) by asserting config
signals. In particular, guest images for the MPS2 AN505 board rely
on the MPS2's initial VTOR being correct for that board.
Implement a QEMU property so board and SoC code can set the reset
value to the correct value.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 3 +++
target/arm/cpu.c | 18 ++++++++++++++----
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4710a43110..72b5668377 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -731,6 +731,9 @@ struct ARMCPU {
*/
uint32_t psci_conduit;
+ /* For v8M, initial value of the Secure VTOR */
+ uint32_t init_svtor;
+
/* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
* QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
*/
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 291ff0b1db..27d9e90308 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -187,6 +187,7 @@ static void arm_cpu_reset(CPUState *s)
uint32_t initial_msp; /* Loaded from 0x0 */
uint32_t initial_pc; /* Loaded from 0x4 */
uint8_t *rom;
+ uint32_t vecbase;
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
env->v7m.secure = true;
@@ -214,8 +215,11 @@ static void arm_cpu_reset(CPUState *s)
/* Unlike A/R profile, M profile defines the reset LR value */
env->regs[14] = 0xffffffff;
- /* Load the initial SP and PC from the vector table at address 0 */
- rom = rom_ptr(0);
+ env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
+
+ /* Load the initial SP and PC from offset 0 and 4 in the vector table
*/
+ vecbase = env->v7m.vecbase[env->v7m.secure];
+ rom = rom_ptr(vecbase);
if (rom) {
/* Address zero is covered by ROM which hasn't yet been
* copied into physical memory.
@@ -228,8 +232,8 @@ static void arm_cpu_reset(CPUState *s)
* it got copied into memory. In the latter case, rom_ptr
* will return a NULL pointer and we should use ldl_phys instead.
*/
- initial_msp = ldl_phys(s->as, 0);
- initial_pc = ldl_phys(s->as, 4);
+ initial_msp = ldl_phys(s->as, vecbase);
+ initial_pc = ldl_phys(s->as, vecbase + 4);
}
env->regs[13] = initial_msp & 0xFFFFFFFC;
@@ -624,6 +628,10 @@ static Property arm_cpu_pmsav7_dregion_property =
pmsav7_dregion,
qdev_prop_uint32, uint32_t);
+/* M profile: initial value of the Secure VTOR */
+static Property arm_cpu_initsvtor_property =
+ DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
+
static void arm_cpu_post_init(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -694,6 +702,8 @@ static void arm_cpu_post_init(Object *obj)
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
+ &error_abort);
}
qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
--
2.16.2
- [Qemu-devel] [PULL 02/39] xlnx-zynqmp-rtc: Add basic time support, (continued)
- [Qemu-devel] [PULL 02/39] xlnx-zynqmp-rtc: Add basic time support, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 05/39] loader: Add new load_ramdisk_as(), Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 07/39] hw/arm/armv7m: Honour CPU's address space for image loads, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 08/39] target/arm: Define an IDAU interface, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 12/39] target/arm: Add Cortex-M33, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 09/39] armv7m: Forward idau property to CPU object, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 11/39] armv7m: Forward init-svtor property to CPU object, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 15/39] qdev: Add new qdev_init_gpio_in_named_with_opaque(), Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 06/39] hw/arm/boot: Honour CPU's address space for image loads, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 13/39] hw/misc/unimp: Move struct to header file, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 10/39] target/arm: Define init-svtor property for the reset secure VTOR value,
Peter Maydell <=
- [Qemu-devel] [PULL 17/39] hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 16/39] hw/core/split-irq: Device that splits IRQ lines, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 14/39] include/hw/or-irq.h: Add missing include guard, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 19/39] hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 21/39] hw/misc/iotkit-secctl: Add remaining simple registers, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 20/39] hw/misc/iotkit-secctl: Add handling for PPCs, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 24/39] target/arm: Add ARM_FEATURE_V8_RDM, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 26/39] target/arm: Refactor disas_simd_indexed size checks, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 25/39] target/arm: Refactor disas_simd_indexed decode, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 18/39] hw/misc/tz-ppc: Model TrustZone peripheral protection controller, Peter Maydell, 2018/03/02