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[Qemu-devel] [PULL 26/39] target/arm: Refactor disas_simd_indexed size c
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 26/39] target/arm: Refactor disas_simd_indexed size checks |
Date: |
Fri, 2 Mar 2018 11:06:27 +0000 |
From: Richard Henderson <address@hidden>
The integer size check was already outside of the opcode switch;
move the floating-point size check outside as well. Unify the
size vs index adjustment between fp and integer paths.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 65 +++++++++++++++++++++++-----------------------
1 file changed, 32 insertions(+), 33 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index fc928b61f6..cbb4510e3a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11820,10 +11820,6 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
case 0x05: /* FMLS */
case 0x09: /* FMUL */
case 0x19: /* FMULX */
- if (size == 1) {
- unallocated_encoding(s);
- return;
- }
is_fp = true;
break;
default:
@@ -11834,45 +11830,48 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
if (is_fp) {
/* convert insn encoded size to TCGMemOp size */
switch (size) {
- case 2: /* single precision */
- size = MO_32;
- index = h << 1 | l;
- rm |= (m << 4);
- break;
- case 3: /* double precision */
- size = MO_64;
- if (l || !is_q) {
+ case 0: /* half-precision */
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
unallocated_encoding(s);
return;
}
- index = h;
- rm |= (m << 4);
- break;
- case 0: /* half precision */
size = MO_16;
- index = h << 2 | l << 1 | m;
- is_fp16 = true;
- if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
- break;
- }
- /* fallthru */
- default: /* unallocated */
- unallocated_encoding(s);
- return;
- }
- } else {
- switch (size) {
- case 1:
- index = h << 2 | l << 1 | m;
break;
- case 2:
- index = h << 1 | l;
- rm |= (m << 4);
+ case MO_32: /* single precision */
+ case MO_64: /* double precision */
break;
default:
unallocated_encoding(s);
return;
}
+ } else {
+ switch (size) {
+ case MO_8:
+ case MO_64:
+ unallocated_encoding(s);
+ return;
+ }
+ }
+
+ /* Given TCGMemOp size, adjust register and indexing. */
+ switch (size) {
+ case MO_16:
+ index = h << 2 | l << 1 | m;
+ break;
+ case MO_32:
+ index = h << 1 | l;
+ rm |= m << 4;
+ break;
+ case MO_64:
+ if (l || !is_q) {
+ unallocated_encoding(s);
+ return;
+ }
+ index = h;
+ rm |= m << 4;
+ break;
+ default:
+ g_assert_not_reached();
}
if (!fp_access_check(s)) {
--
2.16.2
- [Qemu-devel] [PULL 06/39] hw/arm/boot: Honour CPU's address space for image loads, (continued)
- [Qemu-devel] [PULL 06/39] hw/arm/boot: Honour CPU's address space for image loads, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 13/39] hw/misc/unimp: Move struct to header file, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 10/39] target/arm: Define init-svtor property for the reset secure VTOR value, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 17/39] hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 16/39] hw/core/split-irq: Device that splits IRQ lines, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 14/39] include/hw/or-irq.h: Add missing include guard, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 19/39] hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 21/39] hw/misc/iotkit-secctl: Add remaining simple registers, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 20/39] hw/misc/iotkit-secctl: Add handling for PPCs, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 24/39] target/arm: Add ARM_FEATURE_V8_RDM, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 26/39] target/arm: Refactor disas_simd_indexed size checks,
Peter Maydell <=
- [Qemu-devel] [PULL 25/39] target/arm: Refactor disas_simd_indexed decode, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 18/39] hw/misc/tz-ppc: Model TrustZone peripheral protection controller, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 28/39] target/arm: Decode aa64 armv8.1 three same extra, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 22/39] hw/arm/iotkit: Model Arm IOT Kit, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 34/39] target/arm: Decode aa64 armv8.3 fcadd, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 39/39] target/arm: Enable ARM_FEATURE_V8_FCMA, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 29/39] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 23/39] mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 27/39] target/arm: Decode aa64 armv8.1 scalar three same extra, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 32/39] target/arm: Enable ARM_FEATURE_V8_RDM, Peter Maydell, 2018/03/02