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[Qemu-devel] [PULL 31/39] target/arm: Decode aa32 armv8.1 two reg and a
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 31/39] target/arm: Decode aa32 armv8.1 two reg and a scalar |
Date: |
Fri, 2 Mar 2018 11:06:32 +0000 |
From: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 46 ++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 42 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 05fa6a53f9..9169b6b367 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -76,6 +76,10 @@ static const char *regnames[] =
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
+/* Function prototypes for gen_ functions calling Neon helpers. */
+typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
+ TCGv_i32, TCGv_i32);
+
/* initialize TCG globals. */
void arm_translate_init(void)
{
@@ -6985,11 +6989,45 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
}
neon_store_reg64(cpu_V0, rd + pass);
}
-
-
break;
- default: /* 14 and 15 are RESERVED */
- return 1;
+ case 14: /* VQRDMLAH scalar */
+ case 15: /* VQRDMLSH scalar */
+ {
+ NeonGenThreeOpEnvFn *fn;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
+ return 1;
+ }
+ if (u && ((rd | rn) & 1)) {
+ return 1;
+ }
+ if (op == 14) {
+ if (size == 1) {
+ fn = gen_helper_neon_qrdmlah_s16;
+ } else {
+ fn = gen_helper_neon_qrdmlah_s32;
+ }
+ } else {
+ if (size == 1) {
+ fn = gen_helper_neon_qrdmlsh_s16;
+ } else {
+ fn = gen_helper_neon_qrdmlsh_s32;
+ }
+ }
+
+ tmp2 = neon_get_scalar(size, rm);
+ for (pass = 0; pass < (u ? 4 : 2); pass++) {
+ tmp = neon_load_reg(rn, pass);
+ tmp3 = neon_load_reg(rd, pass);
+ fn(tmp, cpu_env, tmp, tmp2, tmp3);
+ tcg_temp_free_i32(tmp3);
+ neon_store_reg(rd, pass, tmp);
+ }
+ tcg_temp_free_i32(tmp2);
+ }
+ break;
+ default:
+ g_assert_not_reached();
}
}
} else { /* size == 3 */
--
2.16.2
- [Qemu-devel] [PULL 25/39] target/arm: Refactor disas_simd_indexed decode, (continued)
- [Qemu-devel] [PULL 25/39] target/arm: Refactor disas_simd_indexed decode, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 18/39] hw/misc/tz-ppc: Model TrustZone peripheral protection controller, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 28/39] target/arm: Decode aa64 armv8.1 three same extra, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 22/39] hw/arm/iotkit: Model Arm IOT Kit, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 34/39] target/arm: Decode aa64 armv8.3 fcadd, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 39/39] target/arm: Enable ARM_FEATURE_V8_FCMA, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 29/39] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 23/39] mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 27/39] target/arm: Decode aa64 armv8.1 scalar three same extra, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 32/39] target/arm: Enable ARM_FEATURE_V8_RDM, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 31/39] target/arm: Decode aa32 armv8.1 two reg and a scalar,
Peter Maydell <=
- [Qemu-devel] [PULL 35/39] target/arm: Decode aa64 armv8.3 fcmla, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 30/39] target/arm: Decode aa32 armv8.1 three same, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 36/39] target/arm: Decode aa32 armv8.3 3-same, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 38/39] target/arm: Decode t32 simd 3reg and 2reg_scalar extension, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 37/39] target/arm: Decode aa32 armv8.3 2-reg-index, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 33/39] target/arm: Add ARM_FEATURE_V8_FCMA, Peter Maydell, 2018/03/02
- Re: [Qemu-devel] [PULL 00/39] target-arm queue, no-reply, 2018/03/02
- Re: [Qemu-devel] [PULL 00/39] target-arm queue, Peter Maydell, 2018/03/02