Re: [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets

[Michael Clark]

On Tue, 6 Mar 2018 at 3:57 PM, Emilio G. Cota <address@hidden> wrote:

> On Tue, Mar 06, 2018 at 12:57:13 +1300, Michael Clark wrote:
> > On Fri, Mar 2, 2018 at 11:53 AM, Emilio G. Cota <address@hidden> wrote:
> >
> > > [ What is this all about? See this message:
> > >   http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
> (snip)
> > > You can fetch this series from:
> > >   https://github.com/cota/qemu/tree/trloop-conv-v1
> >
> >
> > Curious to know what we would need to change in RISC-V translate.c:
> >
> > -
> >
> https://github.com/riscv/riscv-qemu/blob/qemu-upstream-v8/target/riscv/translate.c
> >
> > I'm going to make a v8.1 branch and tag that is a rebase of the v8 patch
> > series against current QEMU master, and hopefully we get the RISC-V port
> > merged before the soft-freeze. Fingers crossed.
>
> I have patches that convert riscv as well.
>
> Once riscv is on master I'll send the patches to the list; I don't want
> this work to delay the riscv merge even more!


Appreciated. Thanks very much!

Michael

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