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Re: [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal instructio
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal instruction in |
Date: |
Tue, 6 Mar 2018 20:09:05 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 03/06/2018 05:43 PM, Michael Clark wrote:
> This was added to help debug issues using -d in_asm. It is
> useful to see the instruction bytes, as one can detect if
> one is trying to execute ASCII or device-tree magic.
clean :)
>
> Signed-off-by: Michael Clark <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> disas/riscv.c | 39 ++++++++++++++++++++-------------------
> 1 file changed, 20 insertions(+), 19 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 3c17501..4580308 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2769,25 +2769,6 @@ static void format_inst(char *buf, size_t buflen,
> size_t tab, rv_decode *dec)
> char tmp[64];
> const char *fmt;
>
> - if (dec->op == rv_op_illegal) {
> - size_t len = inst_length(dec->inst);
> - switch (len) {
> - case 2:
> - snprintf(buf, buflen, "(0x%04" PRIx64 ")", dec->inst);
> - break;
> - case 4:
> - snprintf(buf, buflen, "(0x%08" PRIx64 ")", dec->inst);
> - break;
> - case 6:
> - snprintf(buf, buflen, "(0x%012" PRIx64 ")", dec->inst);
> - break;
> - default:
> - snprintf(buf, buflen, "(0x%016" PRIx64 ")", dec->inst);
> - break;
> - }
> - return;
> - }
> -
> fmt = opcode_data[dec->op].format;
> while (*fmt) {
> switch (*fmt) {
> @@ -3004,6 +2985,11 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa,
> uint64_t pc, rv_inst inst)
> format_inst(buf, buflen, 16, &dec);
> }
>
> +#define INST_FMT_2 "%04" PRIx64 " "
> +#define INST_FMT_4 "%08" PRIx64 " "
> +#define INST_FMT_6 "%012" PRIx64 " "
> +#define INST_FMT_8 "%016" PRIx64 " "
> +
> static int
> print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
> {
> @@ -3031,6 +3017,21 @@ print_insn_riscv(bfd_vma memaddr, struct
> disassemble_info *info, rv_isa isa)
> }
> }
>
> + switch (len) {
> + case 2:
> + (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
> + break;
> + case 4:
> + (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
> + break;
> + case 6:
> + (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
> + break;
> + default:
> + (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
> + break;
> + }
> +
> disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
> (*info->fprintf_func)(info->stream, "%s", buf);
>
>
- [Qemu-devel] [PATCH v1 03/22] RISC-V: Make virt board description match spike, (continued)
- [Qemu-devel] [PATCH v1 03/22] RISC-V: Make virt board description match spike, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 04/22] RISC-V: Use ROM base address and size from memory, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 05/22] RISC-V: Remove redundant identity_translate from, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 06/22] RISC-V: Mark ROM read-only after copying in code and, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions from, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 08/22] RISC-V: Make sure the emulated rom has space for, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal instruction in, Michael Clark, 2018/03/06
- Re: [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal instruction in,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v1 11/22] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 10/22] RISC-V: Hold rcu_read_lock when accessing memory, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 12/22] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 13/22] RISC-V: Make spike and virt header guards more, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 15/22] RISC-V: Use memory_region_is_ram in atomic pte, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 14/22] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection from, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case statement with, Michael Clark, 2018/03/06