Re: [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps

[Alistair Francis]

On Wed, Apr 25, 2018 at 5:08 PM Michael Clark <address@hidden> wrote:

> Vectored traps for asynchrounous interrupts are optional.
> The mtvec/stvec mode field is WARL and hence does not trap
> if an illegal value is written. Illegal values are ignored.

> Later we can add RISCV_FEATURE_VECTORED_TRAPS however
> until then the correct behavior for WARL (Write Any, Read
> Legal) fields is to drop writes to unsupported bits.

> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> ---
>   target/riscv/op_helper.c | 14 ++++++--------
>   1 file changed, 6 insertions(+), 8 deletions(-)

> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 101dac1..828f20c 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -276,11 +276,10 @@ void csr_write_helper(CPURISCVState *env,
target_ulong val_to_write,
>           env->sepc = val_to_write;
>           break;
>       case CSR_STVEC:
> -        if (val_to_write & 1) {
> -            qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not
supported");

Should the unimplemented log be removed?

Alistair

> -            goto do_illegal;
> +        /* we do not support vectored traps for asynchrounous interrupts
*/
> +        if ((val_to_write & 3) == 0) {
> +            env->stvec = val_to_write >> 2 << 2;
>           }
> -        env->stvec = val_to_write >> 2 << 2;
>           break;
>       case CSR_SCOUNTEREN:
>           env->scounteren = val_to_write;
> @@ -298,11 +297,10 @@ void csr_write_helper(CPURISCVState *env,
target_ulong val_to_write,
>           env->mepc = val_to_write;
>           break;
>       case CSR_MTVEC:
> -        if (val_to_write & 1) {
> -            qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not
supported");
> -            goto do_illegal;
> +        /* we do not support vectored traps for asynchrounous interrupts
*/
> +        if ((val_to_write & 3) == 0) {
> +            env->mtvec = val_to_write >> 2 << 2;
>           }
> -        env->mtvec = val_to_write >> 2 << 2;
>           break;
>       case CSR_MCOUNTEREN:
>           env->mcounteren = val_to_write;
> --
> 2.7.0