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Re: [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update P
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps |
Date: |
Thu, 26 Apr 2018 14:14:37 -1000 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 |
On 04/25/2018 01:45 PM, Michael Clark wrote:
> + uint32_t old, new;
> + do {
> + old = atomic_read(&plic->pending[word]);
> + new = (old & ~(1 << (irq & 31))) | (-!!pending & (1 << (irq & 31)));
> + } while (atomic_cmpxchg(&plic->pending[word], old, new) != old);
I prefer
uint32_t old, new, cmp = atomic_read(...);
do {
old = cmp;
new = ...;
cmp = atomic_cmpxchg(...);
} while (old != cmp);
to avoid an extra load, should we loop.
That said, what you have is not wrong. So,
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps, (continued)
- [Qemu-devel] [PATCH v8 17/35] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Michael Clark, 2018/04/25
- Re: [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps,
Richard Henderson <=
- [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 26/35] RISC-V: Update CSR and interrupt definitions, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 28/35] RISC-V: Implement atomic mip/sip CSR updates, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 27/35] RISC-V: Implement modular CSR helper interface, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 29/35] RISC-V: Implement existential predicates for CSRs, Michael Clark, 2018/04/25