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[Qemu-devel] [PATCH v1 19/29] target-microblaze: dec_msr: Fix MTS to FSR
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 19/29] target-microblaze: dec_msr: Fix MTS to FSR |
Date: |
Thu, 3 May 2018 11:19:12 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Fix moves to FSR. Not only bit 31 is accessible.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 05449fb941..97d7782bc6 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -533,11 +533,9 @@ static void dec_msr(DisasContext *dc)
break;
case SR_EAR:
case SR_ESR:
+ case SR_FSR:
tcg_gen_mov_i32(cpu_SR[sr], cpu_R[dc->ra]);
break;
- case 0x7:
- tcg_gen_andi_i32(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
- break;
case 0x800:
tcg_gen_st_i32(cpu_R[dc->ra],
cpu_env, offsetof(CPUMBState, slr));
--
2.14.1
- Re: [Qemu-devel] [PATCH v1 13/29] target-microblaze: Use TCGv for load/store addresses, (continued)
- [Qemu-devel] [PATCH v1 16/29] target-microblaze: Break out trap_illegal(), Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 18/29] target-microblaze: dec_msr: Reuse more code when reg-decoding, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 21/29] target-microblaze: Setup for 64bit addressing, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 19/29] target-microblaze: dec_msr: Fix MTS to FSR,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v1 23/29] target-microblaze: Implement MFSE EAR, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 20/29] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 24/29] target-microblaze: mmu: Add R_TBLX_MISS macros, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 27/29] target-microblaze: mmu: Add a configurable output address mask, Edgar E. Iglesias, 2018/05/03