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[Qemu-devel] [PATCH v1 23/29] target-microblaze: Implement MFSE EAR
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 23/29] target-microblaze: Implement MFSE EAR |
Date: |
Thu, 3 May 2018 11:19:16 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Implement MFSE EAR to enable access to the upper part of EAR.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 0ea100322c..65faa9b97f 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -459,7 +459,7 @@ static void dec_msr(DisasContext *dc)
CPUState *cs = CPU(dc->cpu);
TCGv_i32 t0, t1;
unsigned int sr, rn;
- bool to, clrset;
+ bool to, clrset, extended;
sr = extract32(dc->imm, 0, 14);
to = extract32(dc->imm, 14, 1);
@@ -467,6 +467,9 @@ static void dec_msr(DisasContext *dc)
dc->type_b = 1;
if (to) {
dc->cpustate_changed = 1;
+ extended = extract32(dc->imm, 24, 1);
+ } else {
+ extended = extract32(dc->imm, 19, 1);
}
/* msrclr and msrset. */
@@ -559,6 +562,10 @@ static void dec_msr(DisasContext *dc)
msr_read(dc, cpu_R[dc->rd]);
break;
case SR_EAR:
+ if (extended) {
+ tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_SR[sr]);
+ break;
+ }
case SR_ESR:
case SR_FSR:
case SR_BTR:
--
2.14.1
- [Qemu-devel] [PATCH v1 16/29] target-microblaze: Break out trap_illegal(), (continued)
- [Qemu-devel] [PATCH v1 16/29] target-microblaze: Break out trap_illegal(), Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 18/29] target-microblaze: dec_msr: Reuse more code when reg-decoding, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 21/29] target-microblaze: Setup for 64bit addressing, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 19/29] target-microblaze: dec_msr: Fix MTS to FSR, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 23/29] target-microblaze: Implement MFSE EAR,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v1 20/29] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 24/29] target-microblaze: mmu: Add R_TBLX_MISS macros, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 27/29] target-microblaze: mmu: Add a configurable output address mask, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 25/29] target-microblaze: mmu: Remove unused register state, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 28/29] target-microblaze: Add support for extended access to TLBLO, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 26/29] target-microblaze: mmu: Prepare for 64-bit addresses, Edgar E. Iglesias, 2018/05/03