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[Qemu-devel] [PULL 13/21] target/riscv: Use new atomic min/max expanders
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/21] target/riscv: Use new atomic min/max expanders |
Date: |
Thu, 10 May 2018 18:45:11 +0100 |
From: Richard Henderson <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/riscv/translate.c | 72 +++++++++++-----------------------------
1 file changed, 20 insertions(+), 52 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c0e6a044d3..0d19ecc733 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -724,7 +724,6 @@ static void gen_atomic(DisasContext *ctx, uint32_t opc,
TCGv src1, src2, dat;
TCGLabel *l1, *l2;
TCGMemOp mop;
- TCGCond cond;
bool aq, rl;
/* Extract the size of the atomic operation. */
@@ -822,60 +821,29 @@ static void gen_atomic(DisasContext *ctx, uint32_t opc,
tcg_gen_atomic_fetch_or_tl(src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(rd, src2);
break;
-
case OPC_RISC_AMOMIN:
- cond = TCG_COND_LT;
- goto do_minmax;
- case OPC_RISC_AMOMAX:
- cond = TCG_COND_GT;
- goto do_minmax;
- case OPC_RISC_AMOMINU:
- cond = TCG_COND_LTU;
- goto do_minmax;
- case OPC_RISC_AMOMAXU:
- cond = TCG_COND_GTU;
- goto do_minmax;
- do_minmax:
- /* Handle the RL barrier. The AQ barrier is handled along the
- parallel path by the SC atomic cmpxchg. On the serial path,
- of course, barriers do not matter. */
- if (rl) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- }
- if (tb_cflags(ctx->tb) & CF_PARALLEL) {
- l1 = gen_new_label();
- gen_set_label(l1);
- } else {
- l1 = NULL;
- }
-
gen_get_gpr(src1, rs1);
gen_get_gpr(src2, rs2);
- if ((mop & MO_SSIZE) == MO_SL) {
- /* Sign-extend the register comparison input. */
- tcg_gen_ext32s_tl(src2, src2);
- }
- dat = tcg_temp_local_new();
- tcg_gen_qemu_ld_tl(dat, src1, ctx->mem_idx, mop);
- tcg_gen_movcond_tl(cond, src2, dat, src2, dat, src2);
-
- if (tb_cflags(ctx->tb) & CF_PARALLEL) {
- /* Parallel context. Make this operation atomic by verifying
- that the memory didn't change while we computed the result. */
- tcg_gen_atomic_cmpxchg_tl(src2, src1, dat, src2, ctx->mem_idx,
mop);
-
- /* If the cmpxchg failed, retry. */
- /* ??? There is an assumption here that this will eventually
- succeed, such that we don't live-lock. This is not unlike
- a similar loop that the compiler would generate for e.g.
- __atomic_fetch_and_xor, so don't worry about it. */
- tcg_gen_brcond_tl(TCG_COND_NE, dat, src2, l1);
- } else {
- /* Serial context. Directly store the result. */
- tcg_gen_qemu_st_tl(src2, src1, ctx->mem_idx, mop);
- }
- gen_set_gpr(rd, dat);
- tcg_temp_free(dat);
+ tcg_gen_atomic_fetch_smin_tl(src2, src1, src2, ctx->mem_idx, mop);
+ gen_set_gpr(rd, src2);
+ break;
+ case OPC_RISC_AMOMAX:
+ gen_get_gpr(src1, rs1);
+ gen_get_gpr(src2, rs2);
+ tcg_gen_atomic_fetch_smax_tl(src2, src1, src2, ctx->mem_idx, mop);
+ gen_set_gpr(rd, src2);
+ break;
+ case OPC_RISC_AMOMINU:
+ gen_get_gpr(src1, rs1);
+ gen_get_gpr(src2, rs2);
+ tcg_gen_atomic_fetch_umin_tl(src2, src1, src2, ctx->mem_idx, mop);
+ gen_set_gpr(rd, src2);
+ break;
+ case OPC_RISC_AMOMAXU:
+ gen_get_gpr(src1, rs1);
+ gen_get_gpr(src2, rs2);
+ tcg_gen_atomic_fetch_umax_tl(src2, src1, src2, ctx->mem_idx, mop);
+ gen_set_gpr(rd, src2);
break;
default:
--
2.17.0
- [Qemu-devel] [PULL 07/21] atomic.h: Work around gcc spurious "unused value" warning, (continued)
- [Qemu-devel] [PULL 07/21] atomic.h: Work around gcc spurious "unused value" warning, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 08/21] tcg: Introduce helpers for integer min/max, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 06/21] make sure that we aren't overwriting mc->get_hotplug_handler by accident, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 09/21] target/arm: Use new min/max expanders, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 10/21] target/xtensa: Use new min/max expanders, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 05/21] arm/boot: split load_dtb() from arm_load_kernel(), Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 12/21] tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 11/21] tcg: Introduce atomic helpers for integer min/max, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 04/21] platform-bus-device: use device plug callback instead of machine_done notifier, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 15/21] target/arm: Fill in disas_ldst_atomic, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 13/21] target/riscv: Use new atomic min/max expanders,
Peter Maydell <=
- [Qemu-devel] [PULL 17/21] target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 16/21] target/arm: Implement CAS and CASP, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 18/21] target/arm: Implement vector shifted SCVF/UCVF for fp16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 14/21] target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 20/21] target/arm: Fix float16 to/from int16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 19/21] target/arm: Implement vector shifted FCVT for fp16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 21/21] target/arm: Clear SVE high bits for FMOV, Peter Maydell, 2018/05/10
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, no-reply, 2018/05/10
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, Peter Maydell, 2018/05/14