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[Qemu-devel] [PULL 21/21] target/arm: Clear SVE high bits for FMOV
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 21/21] target/arm: Clear SVE high bits for FMOV |
Date: |
Thu, 10 May 2018 18:45:19 +0100 |
From: Richard Henderson <address@hidden>
Use write_fp_dreg and clear_vec_high to zero the bits
that need zeroing for these cases.
Cc: address@hidden
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b302171545..b0471c842e 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5681,31 +5681,24 @@ static void handle_fmov(DisasContext *s, int rd, int
rn, int type, bool itof)
if (itof) {
TCGv_i64 tcg_rn = cpu_reg(s, rn);
+ TCGv_i64 tmp;
switch (type) {
case 0:
- {
/* 32 bit */
- TCGv_i64 tmp = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
tcg_gen_ext32u_i64(tmp, tcg_rn);
- tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64));
- tcg_gen_movi_i64(tmp, 0);
- tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
+ write_fp_dreg(s, rd, tmp);
tcg_temp_free_i64(tmp);
break;
- }
case 1:
- {
/* 64 bit */
- TCGv_i64 tmp = tcg_const_i64(0);
- tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64));
- tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
- tcg_temp_free_i64(tmp);
+ write_fp_dreg(s, rd, tcg_rn);
break;
- }
case 2:
/* 64 bit to top half. */
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
+ clear_vec_high(s, true, rd);
break;
}
} else {
--
2.17.0
- [Qemu-devel] [PULL 11/21] tcg: Introduce atomic helpers for integer min/max, (continued)
- [Qemu-devel] [PULL 11/21] tcg: Introduce atomic helpers for integer min/max, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 04/21] platform-bus-device: use device plug callback instead of machine_done notifier, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 15/21] target/arm: Fill in disas_ldst_atomic, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 13/21] target/riscv: Use new atomic min/max expanders, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 17/21] target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 16/21] target/arm: Implement CAS and CASP, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 18/21] target/arm: Implement vector shifted SCVF/UCVF for fp16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 14/21] target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 20/21] target/arm: Fix float16 to/from int16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 19/21] target/arm: Implement vector shifted FCVT for fp16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 21/21] target/arm: Clear SVE high bits for FMOV,
Peter Maydell <=
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, no-reply, 2018/05/10
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, Peter Maydell, 2018/05/14