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Re: [Qemu-devel] [PATCH v2 5/7] hw/riscv/sifive_u: Set the interrupt con
From: |
Michael Clark |
Subject: |
Re: [Qemu-devel] [PATCH v2 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts |
Date: |
Sat, 12 May 2018 21:20:34 +1200 |
On Sat, May 12, 2018 at 11:28 AM, Alistair Francis <address@hidden
> wrote:
> Set the interrupt-controller ndev to the correct number taken from the
> HiFive Unleashed board.
>
> Signed-off-by: Alistair Francis <address@hidden>
>
If you look at hw/riscv/virt.c we have removed hardcoding a few more
constants using in the device tree. e.g. we allocate and resolve phandles
vs hardcoding them. We can alwauys make a follow up commits to move some of
these magic numbers into constants in the headers, preferably with enum vs
#define.
Reviewed-by: Michael Clark <address@hidden>
---
> hw/riscv/sifive_u.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 859f43c6f9..50389cdc90 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -187,7 +187,7 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> 0x0, memmap[SIFIVE_U_PLIC].size);
> qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
> - qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4);
> + qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
> qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
> qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
> plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
> --
> 2.17.0
>
>
- [Qemu-devel] [PATCH v2 0/7] RISC-V: SoCify SiFive boards and connect GEM, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 1/7] hw/riscv/sifive_u: Create a U54 SoC object, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 2/7] hw/riscv/sifive_e: Create a E31 SoC object, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts, Alistair Francis, 2018/05/11
- Re: [Qemu-devel] [PATCH v2 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts,
Michael Clark <=
- [Qemu-devel] [PATCH v2 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device, Alistair Francis, 2018/05/11