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[Qemu-devel] [PULL 07/32] hw/arm/smmu-common: Fix coverity issue in get_
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 07/32] hw/arm/smmu-common: Fix coverity issue in get_block_pte_address |
Date: |
Fri, 18 May 2018 18:19:44 +0100 |
From: Eric Auger <address@hidden>
Coverity points out that this can overflow if n > 31,
because it's only doing 32-bit arithmetic. Let's use 1ULL instead
of 1. Also the formulae used to compute n can be replaced by
the level_shift() macro.
Reported-by: Peter Maydell <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/smmu-common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 01c7be82b6..3c5f7245b5 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -83,9 +83,9 @@ static inline hwaddr get_table_pte_address(uint64_t pte, int
granule_sz)
static inline hwaddr get_block_pte_address(uint64_t pte, int level,
int granule_sz, uint64_t *bsz)
{
- int n = (granule_sz - 3) * (4 - level) + 3;
+ int n = level_shift(level, granule_sz);
- *bsz = 1 << n;
+ *bsz = 1ULL << n;
return PTE_ADDRESS(pte, n);
}
--
2.17.0
- [Qemu-devel] [PULL 00/32] target-arm queue, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 03/32] target/arm: Add the XML dynamic generation, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 02/32] target/arm: Add "_S" suffix to the secure version of a sysreg, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 05/32] xlnx-zynqmp: Connect the ZynqMP GDMA and ADMA, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 07/32] hw/arm/smmu-common: Fix coverity issue in get_block_pte_address,
Peter Maydell <=
- [Qemu-devel] [PULL 09/32] target/arm: Add SVE decode skeleton, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 06/32] hw/arm/smmuv3: Fix Coverity issue in smmuv3_record_event, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 01/32] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 04/32] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 08/32] target/arm: Introduce translate-a64.h, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 11/32] target/arm: Implement SVE load vector/predicate, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 19/32] target/arm: Implement SVE bitwise shift by wide elements (predicated), Peter Maydell, 2018/05/18