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[Qemu-devel] [PULL 01/32] target/arm: Add "ARM_CP_NO_GDB" as a new bit f
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/32] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type |
Date: |
Fri, 18 May 2018 18:19:38 +0100 |
From: Abdallah Bouassida <address@hidden>
This is a preparation for the coming feature of creating dynamically an XML
description for the ARM sysregs.
A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML.
This bit is enabled automatically when creating CP_ANY wildcard aliases.
This bit could be enabled manually for any register we want to remove from the
dynamic XML description.
Signed-off-by: Abdallah Bouassida <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 3 ++-
target/arm/helper.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3b086be570..c78ccabded 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1821,10 +1821,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
#define ARM_CP_FPU 0x1000
#define ARM_CP_SVE 0x2000
+#define ARM_CP_NO_GDB 0x4000
/* Used only as a terminator for ARMCPRegInfo lists */
#define ARM_CP_SENTINEL 0xffff
/* Mask of only the flag bits in a type field */
-#define ARM_CP_FLAG_MASK 0x30ff
+#define ARM_CP_FLAG_MASK 0x70ff
/* Valid values for ARMCPRegInfo state field, indicating which of
* the AArch32 and AArch64 execution states this register is visible in.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index db8bbe52a6..118422b92c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5678,7 +5678,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
if (((r->crm == CP_ANY) && crm != 0) ||
((r->opc1 == CP_ANY) && opc1 != 0) ||
((r->opc2 == CP_ANY) && opc2 != 0)) {
- r2->type |= ARM_CP_ALIAS;
+ r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
}
/* Check that raw accesses are either forbidden or handled. Note that
--
2.17.0
- [Qemu-devel] [PULL 00/32] target-arm queue, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 03/32] target/arm: Add the XML dynamic generation, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 02/32] target/arm: Add "_S" suffix to the secure version of a sysreg, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 05/32] xlnx-zynqmp: Connect the ZynqMP GDMA and ADMA, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 07/32] hw/arm/smmu-common: Fix coverity issue in get_block_pte_address, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 09/32] target/arm: Add SVE decode skeleton, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 06/32] hw/arm/smmuv3: Fix Coverity issue in smmuv3_record_event, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 01/32] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type,
Peter Maydell <=
- [Qemu-devel] [PULL 04/32] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 08/32] target/arm: Introduce translate-a64.h, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 11/32] target/arm: Implement SVE load vector/predicate, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 19/32] target/arm: Implement SVE bitwise shift by wide elements (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 12/32] target/arm: Implement SVE predicate test, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 13/32] target/arm: Implement SVE Predicate Logical Operations Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 10/32] target/arm: Implement SVE Bitwise Logical - Unpredicated Group, Peter Maydell, 2018/05/18