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Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID featu
From: |
Daniel P . Berrangé |
Subject: |
Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit |
Date: |
Tue, 5 Jun 2018 15:04:53 +0100 |
User-agent: |
Mutt/1.9.5 (2018-04-13) |
On Tue, Jun 05, 2018 at 08:31:41AM -0500, Tom Lendacky wrote:
> On 6/4/2018 3:07 PM, Eduardo Habkost wrote:
> > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote:
> >> AMD future CPUs expose _two_ ways to utilize the Intel equivalant
> >> of the Speculative Store Bypass Disable. The first is via
> >> the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second
> >> is via the SPEC_CTRL MSR (0x48). The document titled:
> >> 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
> >>
> >> gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR.
> >>
> >> A copy of this document is available at
> >> https://bugzilla.kernel.org/show_bug.cgi?id=199889
> >>
> >> Anyhow, this means that on future AMD CPUs there will be _two_ ways to
> >> deal with SSBD.
> >
> > Does anybody know if there are AMD CPUs where virt-ssbd won't
> > work and would require amd-ssbd to mitigate vulnerabilities?
>
> The idea behind virt-ssbd was to provide an architectural method for
> a guest to do SSBD when amd-ssbd isn't present. The amd-ssbd feature
> will use SPEC_CTRL which is intended to not be intercepted and
> will be fast. The use of virt-ssbd will always be intercepted and
> therefore will not be as fast. So a guest should be presented with
> amd-ssbd, if available, in preference to virt-ssbd.
Thanks, that's useful info.
Can you say whether amd-ssbd is going to become available for existing
CPUs via microcode updates, or will it only be present in future CPUs ?
> > Also, do we have kernel arch/x86/kvm/cpuid.c patches, already?
> > I prefer to add new CPUID flag names only after the flag name is
> > already agreed upon on the kernel side.
> >
> >
> >>
> >> Signed-off-by: Konrad Rzeszutek Wilk <address@hidden>
> >> ---
> >> target/i386/cpu.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> >> index 52d334a..f91990c 100644
> >> --- a/target/i386/cpu.c
> >> +++ b/target/i386/cpu.c
> >> @@ -490,7 +490,7 @@ static FeatureWordInfo
> >> feature_word_info[FEATURE_WORDS] = {
> >> "ibpb", NULL, NULL, NULL,
> >> NULL, NULL, NULL, NULL,
> >> NULL, NULL, NULL, NULL,
> >> - NULL, "virt-ssbd", NULL, NULL,
> >> + "amd-ssbd", "virt-ssbd", NULL, NULL,
> >> NULL, NULL, NULL, NULL,
> >> },
> >> .cpuid_eax = 0x80000008,
Regards,
Daniel
--
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- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit, (continued)
- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit, Daniel P . Berrangé, 2018/06/13
- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit, Konrad Rzeszutek Wilk, 2018/06/13
- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit, Daniel P . Berrangé, 2018/06/13
- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit, Konrad Rzeszutek Wilk, 2018/06/13
- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit, Daniel P . Berrangé, 2018/06/13
- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit, Eduardo Habkost, 2018/06/13
- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit, Tom Lendacky, 2018/06/05
- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit,
Daniel P . Berrangé <=
- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit, Daniel P . Berrangé, 2018/06/06
- Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit, Tom Lendacky, 2018/06/08
[Qemu-devel] [PATCH 2/2] i386: Define AMD's no SSB mitigation needed., Konrad Rzeszutek Wilk, 2018/06/01
Re: [Qemu-devel] [PATCH QEMU] Patches for new AMD CPU bits., Eduardo Habkost, 2018/06/13