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[Qemu-devel] [PULL 37/43] aspeed_scu: Implement RNG register
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 37/43] aspeed_scu: Implement RNG register |
Date: |
Fri, 15 Jun 2018 15:25:15 +0100 |
From: Joel Stanley <address@hidden>
The ASPEED SoCs contain a single register that returns random data when
read. This models that register so that guests can use it.
The random number data register has a corresponding control register,
however it returns data regardless of the state of the enabled bit, so
the model follows this behaviour.
When the qcrypto call fails we exit as the guest uses the random number
device to feed it's entropy pool, which is used for cryptographic
purposes.
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/misc/aspeed_scu.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 5e6d5744eec..59315010db9 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -16,6 +16,7 @@
#include "qapi/visitor.h"
#include "qemu/bitops.h"
#include "qemu/log.h"
+#include "crypto/random.h"
#include "trace.h"
#define TO_REG(offset) ((offset) >> 2)
@@ -154,6 +155,19 @@ static const uint32_t
ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
[BMC_DEV_ID] = 0x00002402U
};
+static uint32_t aspeed_scu_get_random(void)
+{
+ Error *err = NULL;
+ uint32_t num;
+
+ if (qcrypto_random_bytes((uint8_t *)&num, sizeof(num), &err)) {
+ error_report_err(err);
+ exit(1);
+ }
+
+ return num;
+}
+
static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
@@ -167,6 +181,12 @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr
offset, unsigned size)
}
switch (reg) {
+ case RNG_DATA:
+ /* On hardware, RNG_DATA works regardless of
+ * the state of the enable bit in RNG_CTRL
+ */
+ s->regs[RNG_DATA] = aspeed_scu_get_random();
+ break;
case WAKEUP_EN:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
--
2.17.1
- [Qemu-devel] [PULL 33/43] target/arm: Implement SVE Integer Compare - Scalars Group, (continued)
- [Qemu-devel] [PULL 33/43] target/arm: Implement SVE Integer Compare - Scalars Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 34/43] target/arm: Implement FDUP/DUP, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 31/43] target/arm: Implement SVE Partition Break Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 28/43] target/arm: Implement SVE Select Vectors Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 41/43] iommu: Add IOMMU index argument to translate method, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 42/43] exec.c: Handle IOMMUs in address_space_translate_for_iotlb(), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 22/43] target/arm: Implement SVE Permute - Interleaving Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 27/43] target/arm: Implement SVE vector splice (predicated), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 35/43] target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 29/43] target/arm: Implement SVE Integer Compare - Vectors Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 37/43] aspeed_scu: Implement RNG register,
Peter Maydell <=
- [Qemu-devel] [PULL 38/43] m25p80: add support for two bytes WRSR for Macronix chips, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 36/43] target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 39/43] iommu: Add IOMMU index concept to IOMMU API, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 32/43] target/arm: Implement SVE Predicate Count Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 40/43] iommu: Add IOMMU index argument to notifier APIs, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 43/43] target/arm: Allow ARMv6-M Thumb2 instructions, Peter Maydell, 2018/06/15
- Re: [Qemu-devel] [PULL 00/43] target-arm queue, Peter Maydell, 2018/06/15