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[Qemu-devel] [PULL 34/43] target/arm: Implement FDUP/DUP
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 34/43] target/arm: Implement FDUP/DUP |
Date: |
Fri, 15 Jun 2018 15:25:12 +0100 |
From: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-sve.c | 37 +++++++++++++++++++++++++++++++++++++
target/arm/sve.decode | 8 ++++++++
2 files changed, 45 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index ae6a504f61b..13d5effff12 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3191,6 +3191,43 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a,
uint32_t insn)
return true;
}
+/*
+ *** SVE Integer Wide Immediate - Unpredicated Group
+ */
+
+static bool trans_FDUP(DisasContext *s, arg_FDUP *a, uint32_t insn)
+{
+ if (a->esz == 0) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ int dofs = vec_full_reg_offset(s, a->rd);
+ uint64_t imm;
+
+ /* Decode the VFP immediate. */
+ imm = vfp_expand_imm(a->esz, a->imm);
+ imm = dup_const(a->esz, imm);
+
+ tcg_gen_gvec_dup64i(dofs, vsz, vsz, imm);
+ }
+ return true;
+}
+
+static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a, uint32_t insn)
+{
+ if (a->esz == 0 && extract32(insn, 13, 1)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ int dofs = vec_full_reg_offset(s, a->rd);
+
+ tcg_gen_gvec_dup64i(dofs, vsz, vsz, dup_const(a->esz, a->imm));
+ }
+ return true;
+}
+
/*
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
*/
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 4b718060a9c..b8bd22aff7a 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -614,6 +614,14 @@ CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1
0000
# SVE integer compare scalar count and limit
WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4
+### SVE Integer Wide Immediate - Unpredicated Group
+
+# SVE broadcast floating-point immediate (unpredicated)
+FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
+
+# SVE broadcast integer immediate (unpredicated)
+DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
+
### SVE Memory - 32-bit Gather and Unsized Contiguous Group
# SVE load predicate register
--
2.17.1
- [Qemu-devel] [PULL 18/43] exec.c: Use stn_p() and ldn_p() instead of explicit switches, (continued)
- [Qemu-devel] [PULL 18/43] exec.c: Use stn_p() and ldn_p() instead of explicit switches, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 19/43] target/arm: Extend vec_reg_offset to larger sizes, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 03/43] hw/sh/sh7750: Convert away from old_mmio, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 20/43] target/arm: Implement SVE Permute - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 25/43] target/arm: Implement SVE copy to vector (predicated), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 24/43] target/arm: Implement SVE conditionally broadcast/extract element, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 02/43] hw/arm/mps2-tz: Put ethernet controller behind PPC, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 26/43] target/arm: Implement SVE reverse within elements, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 30/43] target/arm: Implement SVE Integer Compare - Immediate Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 33/43] target/arm: Implement SVE Integer Compare - Scalars Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 34/43] target/arm: Implement FDUP/DUP,
Peter Maydell <=
- [Qemu-devel] [PULL 31/43] target/arm: Implement SVE Partition Break Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 28/43] target/arm: Implement SVE Select Vectors Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 41/43] iommu: Add IOMMU index argument to translate method, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 42/43] exec.c: Handle IOMMUs in address_space_translate_for_iotlb(), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 22/43] target/arm: Implement SVE Permute - Interleaving Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 27/43] target/arm: Implement SVE vector splice (predicated), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 35/43] target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 29/43] target/arm: Implement SVE Integer Compare - Vectors Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 37/43] aspeed_scu: Implement RNG register, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 38/43] m25p80: add support for two bytes WRSR for Macronix chips, Peter Maydell, 2018/06/15