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[Qemu-devel] [PULL 06/55] hw/arm/virt: Silence dtc /memory warning
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/55] hw/arm/virt: Silence dtc /memory warning |
Date: |
Fri, 29 Jun 2018 15:52:58 +0100 |
From: Eric Auger <address@hidden>
When running dtc on the guest /proc/device-tree we get the
following warning: Warning (unit_address_vs_reg): Node /memory
has a reg or ranges property, but no unit name".
Let's fix that by adding the unit address to the node name. We also
don't create the /memory node anymore in create_fdt(). We directly
create it in load_dtb. /chosen still needs to be created in create_fdt
as the uart needs it. In case the user provided his own dtb, we nop
all memory nodes found in root and create new one(s).
Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/boot.c | 41 +++++++++++++++++++++++------------------
hw/arm/virt.c | 7 +------
2 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 1e481662adb..e09201cc97c 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -490,11 +490,13 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info
*binfo,
hwaddr addr_limit, AddressSpace *as)
{
void *fdt = NULL;
- int size, rc;
+ int size, rc, n = 0;
uint32_t acells, scells;
char *nodename;
unsigned int i;
hwaddr mem_base, mem_len;
+ char **node_path;
+ Error *err = NULL;
if (binfo->dtb_filename) {
char *filename;
@@ -546,12 +548,21 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info
*binfo,
goto fail;
}
+ /* nop all root nodes matching /memory or /address@hidden */
+ node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
+ if (err) {
+ error_report_err(err);
+ goto fail;
+ }
+ while (node_path[n]) {
+ if (g_str_has_prefix(node_path[n], "/memory")) {
+ qemu_fdt_nop_node(fdt, node_path[n]);
+ }
+ n++;
+ }
+ g_strfreev(node_path);
+
if (nb_numa_nodes > 0) {
- /*
- * Turn the /memory node created before into a NOP node, then create
- * /address@hidden nodes for all numa nodes respectively.
- */
- qemu_fdt_nop_node(fdt, "/memory");
mem_base = binfo->loader_start;
for (i = 0; i < nb_numa_nodes; i++) {
mem_len = numa_info[i].node_mem;
@@ -572,24 +583,18 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info
*binfo,
g_free(nodename);
}
} else {
- Error *err = NULL;
+ nodename = g_strdup_printf("/address@hidden" PRIx64,
binfo->loader_start);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
- rc = fdt_path_offset(fdt, "/memory");
- if (rc < 0) {
- qemu_fdt_add_subnode(fdt, "/memory");
- }
-
- if (!qemu_fdt_getprop(fdt, "/memory", "device_type", NULL, &err)) {
- qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
- }
-
- rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg",
+ rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
acells, binfo->loader_start,
scells, binfo->ram_size);
if (rc < 0) {
- fprintf(stderr, "couldn't set /memory/reg\n");
+ fprintf(stderr, "couldn't set %s reg\n", nodename);
goto fail;
}
+ g_free(nodename);
}
rc = fdt_path_offset(fdt, "/chosen");
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 6cce2828f7c..281ddcdf6e2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -204,13 +204,8 @@ static void create_fdt(VirtMachineState *vms)
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
- /*
- * /chosen and /memory nodes must exist for load_dtb
- * to fill in necessary properties later
- */
+ /* /chosen must exist for load_dtb to fill in necessary properties later */
qemu_fdt_add_subnode(fdt, "/chosen");
- qemu_fdt_add_subnode(fdt, "/memory");
- qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
/* Clock node, for the benefit of the UART. The kernel device tree
* binding documentation claims the PL011 node clock properties are
--
2.17.1
- [Qemu-devel] [PULL 00/55] target-arm queue, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 10/55] target/arm: Implement SVE load and broadcast quadword, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 09/55] target/arm: Implement SVE Memory Contiguous Store Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 01/55] hw/block/fdc: Replace error_setg(&error_abort) by assert(), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 05/55] hw/arm/virt: Silence dtc /intc warnings, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 04/55] device_tree: Add qemu_fdt_node_unit_path, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 08/55] target/arm: Implement SVE Contiguous Load, first-fault and no-fault, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 11/55] target/arm: Implement SVE integer convert to floating-point, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 06/55] hw/arm/virt: Silence dtc /memory warning,
Peter Maydell <=
- [Qemu-devel] [PULL 03/55] device_tree: Replace error_setg(&error_fatal) by error_report() + exit(), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 02/55] hw/arm/sysbus-fdt: Replace error_setg(&error_fatal) by error_report() + exit(), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 14/55] target/arm: Implement SVE Floating Point Accumulating Reduction Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 16/55] target/arm: Implement SVE store vector/predicate register, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 07/55] target/arm: Implement SVE Memory Contiguous Load Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 21/55] target/arm: Implement SVE scatter store vector immediate, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 26/55] target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 32/55] target/arm: Implement SVE floating-point unary operations, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 15/55] target/arm: Implement SVE load and broadcast element, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 18/55] target/arm: Implement SVE prefetches, Peter Maydell, 2018/06/29