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[Qemu-devel] [PULL 14/55] target/arm: Implement SVE Floating Point Accum
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 14/55] target/arm: Implement SVE Floating Point Accumulating Reduction Group |
Date: |
Fri, 29 Jun 2018 15:53:06 +0100 |
From: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper-sve.h | 7 +++++
target/arm/sve_helper.c | 56 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sve.c | 45 ++++++++++++++++++++++++++++++
target/arm/sve.decode | 5 ++++
4 files changed, 113 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index eb0645dd432..68e55a8d031 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -720,6 +720,13 @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG,
+ i64, i64, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG,
+ i64, i64, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG,
+ i64, i64, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG,
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 2f416e5e286..2d08b7dcd3d 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2811,6 +2811,62 @@ uint32_t HELPER(sve_while)(void *vd, uint32_t count,
uint32_t pred_desc)
return predtest_ones(d, oprsz, esz_mask);
}
+uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
+ void *status, uint32_t desc)
+{
+ intptr_t i = 0, opr_sz = simd_oprsz(desc);
+ float16 result = nn;
+
+ do {
+ uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
+ do {
+ if (pg & 1) {
+ float16 mm = *(float16 *)(vm + H1_2(i));
+ result = float16_add(result, mm, status);
+ }
+ i += sizeof(float16), pg >>= sizeof(float16);
+ } while (i & 15);
+ } while (i < opr_sz);
+
+ return result;
+}
+
+uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
+ void *status, uint32_t desc)
+{
+ intptr_t i = 0, opr_sz = simd_oprsz(desc);
+ float32 result = nn;
+
+ do {
+ uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
+ do {
+ if (pg & 1) {
+ float32 mm = *(float32 *)(vm + H1_2(i));
+ result = float32_add(result, mm, status);
+ }
+ i += sizeof(float32), pg >>= sizeof(float32);
+ } while (i & 15);
+ } while (i < opr_sz);
+
+ return result;
+}
+
+uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
+ void *status, uint32_t desc)
+{
+ intptr_t i = 0, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *m = vm;
+ uint8_t *pg = vg;
+
+ for (i = 0; i < opr_sz; i++) {
+ if (pg[H1(i)] & 1) {
+ nn = float64_add(nn, m[i], status);
+ }
+ }
+
+ return nn;
+}
+
/* Fully general three-operand expander, controlled by a predicate,
* With the extra float_status parameter.
*/
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 369ce98dc60..ceb46895e0d 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3383,6 +3383,51 @@ DO_ZZI(UMIN, umin)
#undef DO_ZZI
+/*
+ *** SVE Floating Point Accumulating Reduction Group
+ */
+
+static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
+{
+ typedef void fadda_fn(TCGv_i64, TCGv_i64, TCGv_ptr,
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
+ static fadda_fn * const fns[3] = {
+ gen_helper_sve_fadda_h,
+ gen_helper_sve_fadda_s,
+ gen_helper_sve_fadda_d,
+ };
+ unsigned vsz = vec_full_reg_size(s);
+ TCGv_ptr t_rm, t_pg, t_fpst;
+ TCGv_i64 t_val;
+ TCGv_i32 t_desc;
+
+ if (a->esz == 0) {
+ return false;
+ }
+ if (!sve_access_check(s)) {
+ return true;
+ }
+
+ t_val = load_esz(cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz);
+ t_rm = tcg_temp_new_ptr();
+ t_pg = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm));
+ tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
+ t_fpst = get_fpstatus_ptr(a->esz == MO_16);
+ t_desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
+
+ fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
+
+ tcg_temp_free_i32(t_desc);
+ tcg_temp_free_ptr(t_fpst);
+ tcg_temp_free_ptr(t_pg);
+ tcg_temp_free_ptr(t_rm);
+
+ write_fp_dreg(s, a->rd, t_val);
+ tcg_temp_free_i64(t_val);
+ return true;
+}
+
/*
*** SVE Floating Point Arithmetic - Unpredicated Group
*/
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index e8531e28cd7..675b81aaa03 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -676,6 +676,11 @@ UMIN_zzi 00100101 .. 101 011 110 ........ .....
@rdn_i8u
# SVE integer multiply immediate (unpredicated)
MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
+### SVE FP Accumulating Reduction Group
+
+# SVE floating-point serial reduction (predicated)
+FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
+
### SVE Floating Point Arithmetic - Unpredicated Group
# SVE floating-point arithmetic (unpredicated)
--
2.17.1
- [Qemu-devel] [PULL 10/55] target/arm: Implement SVE load and broadcast quadword, (continued)
- [Qemu-devel] [PULL 10/55] target/arm: Implement SVE load and broadcast quadword, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 09/55] target/arm: Implement SVE Memory Contiguous Store Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 01/55] hw/block/fdc: Replace error_setg(&error_abort) by assert(), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 05/55] hw/arm/virt: Silence dtc /intc warnings, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 04/55] device_tree: Add qemu_fdt_node_unit_path, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 08/55] target/arm: Implement SVE Contiguous Load, first-fault and no-fault, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 11/55] target/arm: Implement SVE integer convert to floating-point, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 06/55] hw/arm/virt: Silence dtc /memory warning, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 03/55] device_tree: Replace error_setg(&error_fatal) by error_report() + exit(), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 02/55] hw/arm/sysbus-fdt: Replace error_setg(&error_fatal) by error_report() + exit(), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 14/55] target/arm: Implement SVE Floating Point Accumulating Reduction Group,
Peter Maydell <=
- [Qemu-devel] [PULL 16/55] target/arm: Implement SVE store vector/predicate register, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 07/55] target/arm: Implement SVE Memory Contiguous Load Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 21/55] target/arm: Implement SVE scatter store vector immediate, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 26/55] target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 32/55] target/arm: Implement SVE floating-point unary operations, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 15/55] target/arm: Implement SVE load and broadcast element, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 18/55] target/arm: Implement SVE prefetches, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 17/55] target/arm: Implement SVE scatter stores, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 20/55] target/arm: Implement SVE first-fault gather loads, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 22/55] target/arm: Implement SVE floating-point compare vectors, Peter Maydell, 2018/06/29