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[Qemu-devel] [PATCH v6 09/77] target/mips: Check ELPA flag only in some
From: |
Stefan Markovic |
Subject: |
[Qemu-devel] [PATCH v6 09/77] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 |
Date: |
Thu, 2 Aug 2018 16:15:56 +0200 |
From: Yongbok Kim <address@hidden>
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 841c0c8..bc1f21f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4896,12 +4896,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
{
const char *rn = "invalid";
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
break;
@@ -4912,6 +4911,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
break;
@@ -4964,12 +4964,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *rn = "invalid";
uint64_t mask = ctx->PAMask >> 36;
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
@@ -4981,6 +4980,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
--
1.9.1
- [Qemu-devel] [PATCH v6 00/77] Add nanoMIPS support to QEMU, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 01/77] MAINTAINERS: Update target/mips maintainer's email addresses, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 02/77] target/mips: Avoid case statements formulated by ranges, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 03/77] target/mips: Mark switch fallthroughs with interpretable comments, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 04/77] target/mips: Fix two instances of shadow variables, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 05/77] target/mips: Update some CP0 registers bit definitions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 06/77] target/mips: Add CP0 BadInstrX register, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 07/77] target/mips: Add gen_op_addr_addi(), Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 08/77] target/mips: Don't update BadVAddr register in Debug Mode, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 09/77] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0,
Stefan Markovic <=
- [Qemu-devel] [PATCH v6 10/77] elf: Remove duplicate preprocessor constant definition, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 11/77] elf: Add ELF flags for MIPS machine variants, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 12/77] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 13/77] linux-user: Add preprocessor availability control to some syscalls, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 14/77] target/mips: Add preprocessor constants for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 15/77] target/mips: Add nanoMIPS base instruction set opcodes, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 16/77] target/mips: Add nanoMIPS DSP ASE opcodes, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 17/77] target/mips: Add placeholder and invocation of decode_nanomips_opc(), Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 18/77] target/mips: Add nanoMIPS decoding and extraction utilities, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 19/77] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions, Stefan Markovic, 2018/08/02