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[Qemu-devel] [PATCH 03/20] target/arm: Define ID_AA64ZFR0_EL1
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 03/20] target/arm: Define ID_AA64ZFR0_EL1 |
Date: |
Wed, 8 Aug 2018 21:21:49 -0700 |
Given that the only field defined for this new register may only
be 0, we don't actually need to change anything except the name.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c24c66d43e..61a79e4c44 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4956,9 +4956,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
- { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+ { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
+ /* At present, only SVEver == 0 is defined anyway. */
.resetvalue = 0 },
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
--
2.17.1
- [Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 01/20] target/arm: Set ISAR bits for -cpu max, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 03/20] target/arm: Define ID_AA64ZFR0_EL1,
Richard Henderson <=
- [Qemu-devel] [PATCH 02/20] target/arm: Set ID_AA64PFR0 bits for SVE for -cpu max, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 04/20] target/arm: Adjust sve_exception_el, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 05/20] target/arm: Fix arm_cpu_data_is_big_endian for aa64 user-only, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 06/20] target/arm: Fix arm_current_el for user-only, Richard Henderson, 2018/08/09