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[Qemu-devel] [PULL 06/45] accel/tcg: Handle get_page_addr_code() returni
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/45] accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookups |
Date: |
Tue, 14 Aug 2018 19:17:36 +0100 |
When we support execution from non-RAM MMIO regions, get_page_addr_code()
will return -1 to indicate that there is no RAM at the requested address.
Handle this in the cpu-exec TB hashtable lookup code, treating it as
"no match found".
Note that the call to get_page_addr_code() in tb_lookup_cmp() needs
no changes -- a return of -1 will already correctly result in the
function returning false.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Emilio G. Cota <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
---
accel/tcg/cpu-exec.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index c738b7f7d6e..6bcb6d99bd7 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -332,6 +332,9 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu,
target_ulong pc,
desc.trace_vcpu_dstate = *cpu->trace_dstate;
desc.pc = pc;
phys_pc = get_page_addr_code(desc.env, pc);
+ if (phys_pc == -1) {
+ return NULL;
+ }
desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate);
return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
--
2.18.0
- [Qemu-devel] [PULL 00/45] target-arm queue, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 04/45] nvic: Change NVIC to support ARMv6-M, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 06/45] accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookups,
Peter Maydell <=
- [Qemu-devel] [PULL 08/45] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 03/45] arm: Add ARMv6-M programmer's model support, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 01/45] target/arm: Forbid unprivileged mode for M Baseline, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 14/45] intc/arm_gic: Remove some dead code and put some functions static, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 07/45] accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint(), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 11/45] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 16/45] intc/arm_gic: Add the virtualization extensions to the GIC state, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 28/45] intc/arm_gic: Implement maintenance interrupt generation, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 15/45] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 35/45] target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions, Peter Maydell, 2018/08/14