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[Qemu-devel] [PULL 14/45] intc/arm_gic: Remove some dead code and put so
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 14/45] intc/arm_gic: Remove some dead code and put some functions static |
Date: |
Tue, 14 Aug 2018 19:17:44 +0100 |
From: Luc Michel <address@hidden>
Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.
Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/gic_internal.h | 4 ----
hw/intc/arm_gic.c | 23 ++---------------------
2 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 6f8d242904b..a2075a94dbb 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -75,11 +75,7 @@
/* The special cases for the revision property: */
#define REV_11MPCORE 0
-void gic_set_pending_private(GICState *s, int cpu, int irq);
uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs);
-void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs);
-void gic_update(GICState *s);
-void gic_init_irqs_and_distributor(GICState *s);
void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
MemTxAttrs attrs);
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 53b749d2167..b8eba6e5944 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -71,7 +71,7 @@ static inline bool gic_has_groups(GICState *s)
/* TODO: Many places that call this routine could be optimized. */
/* Update interrupt status after enabled or pending bits have been changed. */
-void gic_update(GICState *s)
+static void gic_update(GICState *s)
{
int best_irq;
int best_prio;
@@ -137,19 +137,6 @@ void gic_update(GICState *s)
}
}
-void gic_set_pending_private(GICState *s, int cpu, int irq)
-{
- int cm = 1 << cpu;
-
- if (gic_test_pending(s, irq, cm)) {
- return;
- }
-
- DPRINTF("Set %d pending cpu %d\n", irq, cpu);
- GIC_DIST_SET_PENDING(irq, cm);
- gic_update(s);
-}
-
static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
int cm, int target)
{
@@ -579,7 +566,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, int
irq, MemTxAttrs attrs)
GIC_DIST_CLEAR_ACTIVE(irq, cm);
}
-void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
+static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
{
int cm = 1 << cpu;
int group;
@@ -1488,12 +1475,6 @@ static const MemoryRegionOps gic_cpu_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-/* This function is used by nvic model */
-void gic_init_irqs_and_distributor(GICState *s)
-{
- gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
-}
-
static void arm_gic_realize(DeviceState *dev, Error **errp)
{
/* Device instance realize function for the GIC sysbus device */
--
2.18.0
- [Qemu-devel] [PULL 00/45] target-arm queue, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 04/45] nvic: Change NVIC to support ARMv6-M, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 06/45] accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookups, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 08/45] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 03/45] arm: Add ARMv6-M programmer's model support, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 01/45] target/arm: Forbid unprivileged mode for M Baseline, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 14/45] intc/arm_gic: Remove some dead code and put some functions static,
Peter Maydell <=
- [Qemu-devel] [PULL 07/45] accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint(), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 11/45] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 16/45] intc/arm_gic: Add the virtualization extensions to the GIC state, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 28/45] intc/arm_gic: Implement maintenance interrupt generation, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 15/45] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 35/45] target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 36/45] target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 10/45] target/arm: Allow execution from small regions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 12/45] intc/arm_gic: Refactor operations on the distributor, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 13/45] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers, Peter Maydell, 2018/08/14