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Re: [Qemu-devel] [Qemu-arm] [PATCH 14/16] hw/dma/pl080: Correct bug in r
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [Qemu-arm] [PATCH 14/16] hw/dma/pl080: Correct bug in register address decode logic |
Date: |
Wed, 15 Aug 2018 16:31:07 +0100 |
On 15 August 2018 at 15:39, Philippe Mathieu-Daudé <address@hidden> wrote:
> On 08/09/2018 10:01 AM, Peter Maydell wrote:
>> diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
>> index a7aacad74f0..8f92550392b 100644
>> --- a/hw/dma/pl080.c
>> +++ b/hw/dma/pl080.c
>> @@ -229,7 +229,7 @@ static uint64_t pl080_read(void *opaque, hwaddr offset,
>> i = (offset & 0xe0) >> 5;
>> if (i >= s->nchannels)
>> goto bad_offset;
>> - switch (offset >> 2) {
>> + switch ((offset >> 2) & 7) {
>
> So only the first channel ever worked...
Not even that -- the per-channel registers are in the
0x100..0x200 region, so channel 0's registers start at 0x100.
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
thanks
-- PMM
- Re: [Qemu-devel] [Qemu-arm] [PATCH 11/16] hw/dma/pl080: Support all three interrupt lines, (continued)
- [Qemu-devel] [PATCH 01/16] hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module, Peter Maydell, 2018/08/09
- [Qemu-devel] [PATCH 12/16] hw/dma/pl080: Don't use CPU address space for DMA accesses, Peter Maydell, 2018/08/09
- [Qemu-devel] [PATCH 08/16] hw/misc/iotkit-secctl: Wire up registers for controlling MSCs, Peter Maydell, 2018/08/09
- [Qemu-devel] [PATCH 14/16] hw/dma/pl080: Correct bug in register address decode logic, Peter Maydell, 2018/08/09
- [Qemu-devel] [PATCH 16/16] hw/arm/mps2-tz: Create PL081s and MSCs, Peter Maydell, 2018/08/09
- Re: [Qemu-devel] [Qemu-arm] [PATCH 00/16] arm: Implement MPS2 watchdogs and DMA, Peter Maydell, 2018/08/16