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[Qemu-devel] [PULL 05/30] target/arm: Reformat integer register dump
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/30] target/arm: Reformat integer register dump |
Date: |
Thu, 16 Aug 2018 14:34:13 +0100 |
From: Richard Henderson <address@hidden>
With PC, there are 33 registers. Three per line lines up nicely
without overflowing 80 columns.
Cc: address@hidden (3.0.1)
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 45a6c2a3aa1..358f169c755 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -137,14 +137,13 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
int el = arm_current_el(env);
const char *ns_status;
- cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
- env->pc, env->xregs[31]);
- for (i = 0; i < 31; i++) {
- cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
- if ((i % 4) == 3) {
- cpu_fprintf(f, "\n");
+ cpu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
+ for (i = 0; i < 32; i++) {
+ if (i == 31) {
+ cpu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
} else {
- cpu_fprintf(f, " ");
+ cpu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
+ (i + 2) % 3 ? " " : "\n");
}
}
--
2.18.0
- [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 06/30] target/arm: Dump SVE state if enabled, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 05/30] target/arm: Reformat integer register dump,
Peter Maydell <=
- [Qemu-devel] [PULL 07/30] target/arm: Add sve-max-vq cpu property to -cpu max, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 04/30] target/arm: Fix offset scaling for LD_zprr and ST_zprr, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 10/30] i.MX6UL: Add Freescale i.MX6 UltraLite 14x14 EVK Board, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 02/30] target/arm: Fix sign-extension in sve do_ldr/do_str, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 03/30] target/arm: Fix offset for LD1R instructions, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 08/30] i.MX6UL: Add i.MX6UL specific CCM device, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 09/30] i.MX6UL: Add i.MX6UL SOC, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 11/30] hw/arm: make bitbanded IO optional on ARMv7-M, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 13/30] loader: extract rom_free() function, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 14/30] loader: add rom transaction API, Peter Maydell, 2018/08/16