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[Qemu-devel] [PULL 02/30] target/arm: Fix sign-extension in sve do_ldr/d
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/30] target/arm: Fix sign-extension in sve do_ldr/do_str |
Date: |
Thu, 16 Aug 2018 14:34:10 +0100 |
From: Richard Henderson <address@hidden>
The expression (int) imm + (uint32_t) len_align turns into uint32_t
and thus with negative imm produces a memory operation at the wrong
offset. None of the numbers involved are particularly large, so
change everything to use int.
Cc: address@hidden (3.0.1)
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-sve.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 89efc80ee70..9e63b5f8e55 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4372,12 +4372,11 @@ static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz
*a, uint32_t insn)
* The load should begin at the address Rn + IMM.
*/
-static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len,
- int rn, int imm)
+static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
{
- uint32_t len_align = QEMU_ALIGN_DOWN(len, 8);
- uint32_t len_remain = len % 8;
- uint32_t nparts = len / 8 + ctpop8(len_remain);
+ int len_align = QEMU_ALIGN_DOWN(len, 8);
+ int len_remain = len % 8;
+ int nparts = len / 8 + ctpop8(len_remain);
int midx = get_mem_index(s);
TCGv_i64 addr, t0, t1;
@@ -4458,12 +4457,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs,
uint32_t len,
}
/* Similarly for stores. */
-static void do_str(DisasContext *s, uint32_t vofs, uint32_t len,
- int rn, int imm)
+static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
{
- uint32_t len_align = QEMU_ALIGN_DOWN(len, 8);
- uint32_t len_remain = len % 8;
- uint32_t nparts = len / 8 + ctpop8(len_remain);
+ int len_align = QEMU_ALIGN_DOWN(len, 8);
+ int len_remain = len % 8;
+ int nparts = len / 8 + ctpop8(len_remain);
int midx = get_mem_index(s);
TCGv_i64 addr, t0;
--
2.18.0
- [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 06/30] target/arm: Dump SVE state if enabled, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 05/30] target/arm: Reformat integer register dump, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 07/30] target/arm: Add sve-max-vq cpu property to -cpu max, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 04/30] target/arm: Fix offset scaling for LD_zprr and ST_zprr, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 10/30] i.MX6UL: Add Freescale i.MX6 UltraLite 14x14 EVK Board, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 02/30] target/arm: Fix sign-extension in sve do_ldr/do_str,
Peter Maydell <=
- [Qemu-devel] [PULL 03/30] target/arm: Fix offset for LD1R instructions, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 08/30] i.MX6UL: Add i.MX6UL specific CCM device, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 09/30] i.MX6UL: Add i.MX6UL SOC, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 11/30] hw/arm: make bitbanded IO optional on ARMv7-M, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 13/30] loader: extract rom_free() function, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 14/30] loader: add rom transaction API, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 16/30] Add QTest testcase for the Intel Hexadecimal, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 20/30] aspeed_sdmc: Set 'cache initial sequence' always true, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 21/30] aspeed_sdmc: Init status always idle, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 12/30] target/arm: add "cortex-m0" CPU model, Peter Maydell, 2018/08/16