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[Qemu-devel] [PULL 21/30] aspeed_sdmc: Init status always idle
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 21/30] aspeed_sdmc: Init status always idle |
Date: |
Thu, 16 Aug 2018 14:34:29 +0100 |
From: Joel Stanley <address@hidden>
The ast2500 SDRAM training routine busy waits on the 'init cycle busy
state' bit in DDR PHY Control/Status register #1 (MCR60).
This ensures the bit always reads zero, and allows training to
complete with upstream u-boot on the ast2500-evb.
Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/misc/aspeed_sdmc.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 9ece545c4ff..522e01ef8c0 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -23,6 +23,10 @@
/* Configuration Register */
#define R_CONF (0x04 / 4)
+/* Control/Status Register #1 (ast2500) */
+#define R_STATUS1 (0x60 / 4)
+#define PHY_BUSY_STATE BIT(0)
+
/*
* Configuration register Ox4 (for Aspeed AST2400 SOC)
*
@@ -137,6 +141,17 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr,
uint64_t data,
g_assert_not_reached();
}
}
+ if (s->silicon_rev == AST2500_A0_SILICON_REV ||
+ s->silicon_rev == AST2500_A1_SILICON_REV) {
+ switch (addr) {
+ case R_STATUS1:
+ /* Will never return 'busy' */
+ data &= ~PHY_BUSY_STATE;
+ break;
+ default:
+ break;
+ }
+ }
s->regs[addr] = data;
}
--
2.18.0
- [Qemu-devel] [PULL 10/30] i.MX6UL: Add Freescale i.MX6 UltraLite 14x14 EVK Board, (continued)
- [Qemu-devel] [PULL 10/30] i.MX6UL: Add Freescale i.MX6 UltraLite 14x14 EVK Board, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 02/30] target/arm: Fix sign-extension in sve do_ldr/do_str, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 03/30] target/arm: Fix offset for LD1R instructions, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 08/30] i.MX6UL: Add i.MX6UL specific CCM device, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 09/30] i.MX6UL: Add i.MX6UL SOC, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 11/30] hw/arm: make bitbanded IO optional on ARMv7-M, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 13/30] loader: extract rom_free() function, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 14/30] loader: add rom transaction API, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 16/30] Add QTest testcase for the Intel Hexadecimal, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 20/30] aspeed_sdmc: Set 'cache initial sequence' always true, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 21/30] aspeed_sdmc: Init status always idle,
Peter Maydell <=
- [Qemu-devel] [PULL 12/30] target/arm: add "cortex-m0" CPU model, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 01/30] target/arm: Fix typo in helper_sve_ld1hss_r, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 22/30] aspeed_sdmc: Handle ECC training, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 25/30] target/arm: Ignore float_flag_input_denormal from fp_status_f16, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 17/30] imx_spi: Unset XCH when TX FIFO becomes empty, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 24/30] target/arm: Adjust FPCR_MASK for FZ16, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 23/30] aspeed: add a max_ram_size property to the memory controller, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 15/30] loader: Implement .hex file loader, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 18/30] aspeed_sdmc: Extend number of valid registers, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 19/30] aspeed_sdmc: Fix saved values, Peter Maydell, 2018/08/16