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[Qemu-devel] [PULL 05/46] target/mips: Add placeholder and invocation of
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 05/46] target/mips: Add placeholder and invocation of decode_nanomips_opc() |
Date: |
Tue, 21 Aug 2018 14:35:10 +0200 |
From: Aleksandar Markovic <address@hidden>
Add empty body and invocation of decode_nanomips_opc() if the bit
ISA_NANOMIPS32 is set in ctx->insn_flags.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7fb322b..4184d91 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16586,6 +16586,19 @@ enum {
NM_EVP = 0x01,
};
+
+/*
+ *
+ * nanoMIPS decoding engine
+ *
+ */
+
+static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+ return 2;
+}
+
+
/* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPS64)
@@ -21402,7 +21415,10 @@ static void mips_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
int is_slot;
is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
- if (!(ctx->hflags & MIPS_HFLAG_M16)) {
+ if (ctx->insn_flags & ISA_NANOMIPS32) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_nanomips_opc(env, ctx);
+ } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
insn_bytes = 4;
decode_opc(env, ctx);
--
2.7.4
- [Qemu-devel] [PULL 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure, (continued)
- [Qemu-devel] [PULL 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 40/46] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 20/46] target/mips: Add emulation of misc nanoMIPS instructions (p_lsx), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 02/46] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 19/46] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 43/46] mips_malta: Add basic nanoMIPS boot code for Malta board, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 35/46] target/mips: Add availability control via bit NMS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 15/46] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 10/46] target/mips: Add emulation of nanoMIPS 16-bit misc instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 05/46] target/mips: Add placeholder and invocation of decode_nanomips_opc(),
Aleksandar Markovic <=
- [Qemu-devel] [PULL 13/46] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 11/46] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 08/46] target/mips: Add emulation of nanoMIPS 16-bit branch instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 16/46] target/mips: Add emulation of nanoMIPS 48-bit instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 21/46] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 30/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 34/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 37/46] target/mips: Add updating BadInstr and BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 33/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 25/46] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/08/21