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[Qemu-devel] [PULL 16/46] target/mips: Add emulation of nanoMIPS 48-bit
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 16/46] target/mips: Add emulation of nanoMIPS 48-bit instructions |
Date: |
Tue, 21 Aug 2018 14:35:21 +0200 |
From: Yongbok Kim <address@hidden>
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and
SWPC48 instructions.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8bc08f7..98df88e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16946,7 +16946,71 @@ static int decode_nanomips_32_48_opc(CPUMIPSState
*env, DisasContext *ctx)
}
break;
case NM_P48I:
- return 6;
+ {
+ insn = cpu_lduw_code(env, ctx->base.pc_next + 4);
+ target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
+ switch (extract32(ctx->opcode, 16, 5)) {
+ case NM_LI48:
+ if (rt != 0) {
+ tcg_gen_movi_tl(cpu_gpr[rt], addr_off);
+ }
+ break;
+ case NM_ADDIU48:
+ if (rt != 0) {
+ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt], addr_off);
+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+ }
+ break;
+ case NM_ADDIUGP48:
+ if (rt != 0) {
+ gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], addr_off);
+ }
+ break;
+ case NM_ADDIUPC48:
+ if (rt != 0) {
+ target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
+ addr_off);
+
+ tcg_gen_movi_tl(cpu_gpr[rt], addr);
+ }
+ break;
+ case NM_LWPC48:
+ if (rt != 0) {
+ TCGv t0;
+ t0 = tcg_temp_new();
+
+ target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
+ addr_off);
+
+ tcg_gen_movi_tl(t0, addr);
+ tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL);
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_SWPC48:
+ {
+ TCGv t0, t1;
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
+ addr_off);
+
+ tcg_gen_movi_tl(t0, addr);
+ gen_load_gpr(t1, rt);
+
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ return 6;
+ }
case NM_P_U12:
switch (extract32(ctx->opcode, 12, 4)) {
case NM_ORI:
--
2.7.4
- [Qemu-devel] [PULL 02/46] target/mips: Add nanoMIPS base instruction set opcodes, (continued)
- [Qemu-devel] [PULL 02/46] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 19/46] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 43/46] mips_malta: Add basic nanoMIPS boot code for Malta board, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 35/46] target/mips: Add availability control via bit NMS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 15/46] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 10/46] target/mips: Add emulation of nanoMIPS 16-bit misc instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 05/46] target/mips: Add placeholder and invocation of decode_nanomips_opc(), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 13/46] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 11/46] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 08/46] target/mips: Add emulation of nanoMIPS 16-bit branch instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 16/46] target/mips: Add emulation of nanoMIPS 48-bit instructions,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 21/46] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 30/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 34/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 37/46] target/mips: Add updating BadInstr and BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 33/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 25/46] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 31/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 17/46] target/mips: Add emulation of nanoMIPS FP instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 39/46] elf: Add EM_NANOMIPS value as a valid one for e_machine field, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 46/46] target/mips: Add definition of nanoMIPS I7200 CPU, Aleksandar Markovic, 2018/08/21