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[Qemu-devel] [PATCH 2/9] hw/intc/arm_gic: Make per-cpu GICH memory regio
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 2/9] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large |
Date: |
Tue, 21 Aug 2018 14:28:04 +0100 |
Reduce the size of the per-cpu GICH memory regions from 0x1000
to 0x200. The registers only cover 0x200 bytes, and the Cortex-A15
wants to map them at a spacing of 0x200 bytes apart. Having the
region be too large interferes with mapping them like that, so
reduce it.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index c1b35fc1ee2..542b4b93eab 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -2084,7 +2084,7 @@ static void arm_gic_realize(DeviceState *dev, Error
**errp)
for (i = 0; i < s->num_cpu; i++) {
memory_region_init_io(&s->vifaceiomem[i + 1], OBJECT(s),
&gic_viface_ops, &s->backref[i],
- "gic_viface", 0x1000);
+ "gic_viface", 0x200);
sysbus_init_mmio(sbd, &s->vifaceiomem[i + 1]);
}
}
--
2.18.0
- [Qemu-devel] [PATCH 7/9] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up, (continued)
- [Qemu-devel] [PATCH 7/9] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up, Peter Maydell, 2018/08/21
- [Qemu-devel] [PATCH 6/9] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/21
- [Qemu-devel] [PATCH 5/9] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/21
- [Qemu-devel] [PATCH 3/9] hw/arm/vexpress: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/21
- [Qemu-devel] [PATCH 4/9] hw/arm/highbank: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/21
- [Qemu-devel] [PATCH 2/9] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large,
Peter Maydell <=
- [Qemu-devel] [PATCH 1/9] hw/intc/arm_gic: Document QEMU interface, Peter Maydell, 2018/08/21