Re: [Qemu-devel] [PATCH v3 3/8] target/mips: Add MXU instructions S32I2M and S32M2I

[Aleksandar Markovic]

> The only commands that have the 5th bit required to address XR16 are 
> S32M2I/S32I2M.
> 
> I can split it out into a separate utility function and put a conditional 
> into the S32M2I/S32I2M functions if you are more comfortable with that.

It is not a bad idea. (preventing all instructions other than S32M2I/S32I2M 
from accessing XR16)

-----Original Message-----
From: Aleksandar Markovic <address@hidden>
Sent: Tuesday, August 28, 2018 12:53 PM
To: Janeczek, Craig <address@hidden>; address@hidden
Cc: address@hidden
Subject: Re: [PATCH v3 3/8] target/mips: Add MXU instructions S32I2M and S32M2I

> > This does not handle the case xra == XR16.

> I do not see where the case is un-handled. XR16 maps to index 15 in the 
> mxu_gpr array.

But, XR16 has its own rules for read/write, and you are treating it just as a 
regular register.