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[Qemu-devel] [PULL 10/33] target/arm: Clear unused predicate bits for LD
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/33] target/arm: Clear unused predicate bits for LD1RQ |
Date: |
Mon, 8 Oct 2018 14:59:41 +0100 |
From: Richard Henderson <address@hidden>
The 16-byte load only uses 16 predicate bits. But while
reusing the other load infrastructure, we find other bits
that are set and trigger an assert. To avoid this and
retain the assert, zero-extend the predicate that we pass
to the LD1 helper.
Tested-by: Laurent Desnogues <address@hidden>
Reported-by: Laurent Desnogues <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-sve.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 667879564f8..4ee3bbca29d 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4765,12 +4765,33 @@ static void do_ldrq(DisasContext *s, int zt, int pg,
TCGv_i64 addr, int msz)
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr t_pg;
TCGv_i32 desc;
+ int poff;
/* Load the first quadword using the normal predicated load helpers. */
desc = tcg_const_i32(simd_desc(16, 16, zt));
- t_pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
+ poff = pred_full_reg_offset(s, pg);
+ if (vsz > 16) {
+ /*
+ * Zero-extend the first 16 bits of the predicate into a temporary.
+ * This avoids triggering an assert making sure we don't have bits
+ * set within a predicate beyond VQ, but we have lowered VQ to 1
+ * for this load operation.
+ */
+ TCGv_i64 tmp = tcg_temp_new_i64();
+#ifdef HOST_WORDS_BIGENDIAN
+ poff += 6;
+#endif
+ tcg_gen_ld16u_i64(tmp, cpu_env, poff);
+
+ poff = offsetof(CPUARMState, vfp.preg_tmp);
+ tcg_gen_st_i64(tmp, cpu_env, poff);
+ tcg_temp_free_i64(tmp);
+ }
+
+ t_pg = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(t_pg, cpu_env, poff);
+
fns[msz](cpu_env, t_pg, addr, desc);
tcg_temp_free_ptr(t_pg);
--
2.19.0
- [Qemu-devel] [PULL 11/33] target/arm: Rewrite helper_sve_ld1*_r using pages, (continued)
- [Qemu-devel] [PULL 11/33] target/arm: Rewrite helper_sve_ld1*_r using pages, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 12/33] target/arm: Rewrite helper_sve_ld[234]*_r, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 14/33] target/arm: Split contiguous loads for endianness, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 16/33] target/arm: Rewrite vector gather loads, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 21/33] target/arm: Define new EXCP type for v8M stack overflows, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 20/33] target/arm: Define new TBFLAG for v8M stack checking, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 19/33] target/arm: Pass TCGMemOpIdx to sve memory helpers, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 17/33] target/arm: Rewrite vector gather stores, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 18/33] target/arm: Rewrite vector gather first-fault loads, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 22/33] target/arm: Move v7m_using_psp() to internals.h, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 10/33] target/arm: Clear unused predicate bits for LD1RQ,
Peter Maydell <=
- [Qemu-devel] [PULL 09/33] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 23/33] target/arm: Add v8M stack checks on ADD/SUB/MOV of SP, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 08/33] target/arm: Handle SVE vector length changes in system mode, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 13/33] target/arm: Rewrite helper_sve_st[1234]*_r, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 32/33] target/arm: Add v8M stack checks for MSR to SP_NS, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 33/33] hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 31/33] target/arm: Add v8M stack checks for VLDM/VSTM, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 29/33] target/arm: Add v8M stack checks for T32 load/store single, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 30/33] target/arm: Add v8M stack checks for Thumb push/pop, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 24/33] target/arm: Add some comments in Thumb decode, Peter Maydell, 2018/10/08