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[Qemu-devel] [PULL 00/10] riscv-pullreq queue
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PULL 00/10] riscv-pullreq queue |
Date: |
Thu, 11 Oct 2018 20:31:38 +0000 |
The following changes since commit 75e50c80e051423a6f55a34ee4a1eec842444a5b:
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-10-10' into
staging (2018-10-11 10:43:37 +0100)
are available in the Git repository at:
address@hidden:alistair23/qemu.git tags/pull-riscv-pullreq-20181011
for you to fetch changes up to f39e645c5f5e9f2b3d41e9c1ad84caae1829cce2:
RISC-V: Don't add NULL bootargs to device-tree (2018-10-11 10:30:26 -0700)
----------------------------------------------------------------
riscv: Connect PCIe and apply some misc patches
Connect PCIe to the RISC-V virt machine and SiFive U machines.
There are also some patches that I have cherry picked from Michael's RISC-V
tree that are ready to be applied.
----------------------------------------------------------------
Alistair Francis (5):
hw/riscv/virt: Increase the number of interrupts
hw/riscv/virt: Connect the gpex PCIe
riscv: Enable VGA and PCIE_VGA
hw/riscv/sifive_u: Connect the Xilinx PCIe
hw/riscv/virt: Connect a VirtIO net PCIe device
Michael Clark (5):
RISC-V: Allow setting and clearing multiple irqs
RISC-V: Move non-ops from op_helper to cpu_helper
RISC-V: Update CSR and interrupt definitions
RISC-V: Add missing free for plic_hart_config
RISC-V: Don't add NULL bootargs to device-tree
default-configs/riscv32-softmmu.mak | 10 +-
default-configs/riscv64-softmmu.mak | 10 +-
hw/riscv/sifive_clint.c | 8 +-
hw/riscv/sifive_plic.c | 4 +-
hw/riscv/sifive_u.c | 68 +++-
hw/riscv/spike.c | 6 +-
hw/riscv/virt.c | 78 +++-
include/hw/riscv/sifive_u.h | 4 +-
include/hw/riscv/virt.h | 6 +-
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.c | 6 +-
target/riscv/cpu.h | 22 +-
target/riscv/cpu_bits.h | 683 +++++++++++++++++---------------
target/riscv/{helper.c => cpu_helper.c} | 35 +-
target/riscv/op_helper.c | 34 +-
15 files changed, 599 insertions(+), 377 deletions(-)
rename target/riscv/{helper.c => cpu_helper.c} (95%)
- [Qemu-devel] [PULL 00/10] riscv-pullreq queue,
Alistair Francis <=
- [Qemu-devel] [PULL 01/10] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 03/10] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 02/10] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 05/10] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 06/10] RISC-V: Allow setting and clearing multiple irqs, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 08/10] RISC-V: Update CSR and interrupt definitions, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 07/10] RISC-V: Move non-ops from op_helper to cpu_helper, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 04/10] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 09/10] RISC-V: Add missing free for plic_hart_config, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 10/10] RISC-V: Don't add NULL bootargs to device-tree, Alistair Francis, 2018/10/11