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Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-ope
From: |
Fredrik Noring |
Subject: |
Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU |
Date: |
Tue, 16 Oct 2018 20:52:50 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Hi Richard,
> > /* global register indices */
> > static TCGv cpu_gpr[32], cpu_PC;
> > static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
> >
> > One option is to create a new array such as
> >
> > static TCGv_i64 mmi_gpr[32];
> >
> > that represents the upper 64 bits of each GPR. Then cpu_gpr must be of
> > a 64-bit type too, even when QEMU runs in 32-bit user mode. The R5900
> > does not implement CP0.Status.UX in hardware, though, so system mode is
> > 64 bits, regardless.
>
> I would not implement r5900 for mips32 in that case,
> I would implement it only for TARGET_MIPS64.
R5900 Linux implements the O32 ABI, which is why 32-bit QEMU user-mode is
very useful. Perhaps a better alternative is to define the MMI registers
as 128-bit, similar to
static TCGv_u128 mmi_gpr[32];
and then copy cpu_gpr to/from mmi_gpr as needed when running the MMIs?
Fredrik
- [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Philippe Mathieu-Daudé, 2018/10/14
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Fredrik Noring, 2018/10/14
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Philippe Mathieu-Daudé, 2018/10/14
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Maciej W. Rozycki, 2018/10/14
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Fredrik Noring, 2018/10/15
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Aleksandar Markovic, 2018/10/16
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Fredrik Noring, 2018/10/16
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Richard Henderson, 2018/10/16
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU,
Fredrik Noring <=
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Maciej W. Rozycki, 2018/10/16
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Aleksandar Markovic, 2018/10/19
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Aleksandar Markovic, 2018/10/28
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Maciej W. Rozycki, 2018/10/28
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Aleksandar Markovic, 2018/10/29
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Fredrik Noring, 2018/10/29
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Aleksandar Markovic, 2018/10/29
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Maciej W. Rozycki, 2018/10/29
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Maciej W. Rozycki, 2018/10/16
- Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU, Fredrik Noring, 2018/10/15