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[Qemu-devel] [PULL 26/27] target/mips: Fix misplaced 'break' in handling
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 26/27] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH |
Date: |
Wed, 17 Oct 2018 14:33:54 +0200 |
From: Stefan Markovic <address@hidden>
Fix misplaced 'break' in handling of NM_SHRA_R_PH. Found by
Coverity (CID 1395627).
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7f97f08..a63509a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -19969,8 +19969,8 @@ static void gen_pool32a5_nanomips_insn(DisasContext
*ctx, int opc,
case 0:
/* SHRA_PH */
gen_helper_shra_ph(v1_t, t0, v1_t);
- break;
gen_store_gpr(v1_t, rt);
+ break;
case 1:
/* SHRA_R_PH */
gen_helper_shra_r_ph(v1_t, t0, v1_t);
--
2.7.4
- [Qemu-devel] [PULL 14/27] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), (continued)
- [Qemu-devel] [PULL 14/27] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 08/27] target/mips: Add a comment before each CP0 register section in cpu.h, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 13/27] target/mips: Increase 'supported ISAs/ASEs' flag holder size, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 06/27] linux-user: Add infrastructure for handling MIPS-specific prctl(), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 11/27] target/mips: Add organizational chart of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 25/27] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 17/27] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 16/27] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 22/27] target/mips: Add CP0 PWCtl register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 26/27] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 12/27] target/mips: Add opcode values of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 18/27] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 15/27] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 21/27] target/mips: Add CP0 PWSize register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 20/27] target/mips: Add CP0 PWField register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 23/27] target/mips: Add reset state for PWSize and PWField registers, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 02/27] elf: Fix PT_MIPS_XXX constants, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 19/27] target/mips: Add CP0 PWBase register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 24/27] target/mips: Implement hardware page table walker for MIPS32, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 03/27] elf: Add MIPS_ABI_FP_XXX constants, Aleksandar Markovic, 2018/10/17