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[Qemu-devel] [PULL 15/27] target/mips: Add bit definitions for DSP R3 AS
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 15/27] target/mips: Add bit definitions for DSP R3 ASE |
Date: |
Wed, 17 Oct 2018 14:33:43 +0200 |
From: Stefan Markovic <address@hidden>
Add DSP R3 ASE related bit definition for insn_flags and hflags.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 1 +
target/mips/mips-defs.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3b3509c..7f4e6d0 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -795,6 +795,7 @@ struct CPUMIPSState {
/* MIPS DSP resources access. */
#define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */
#define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
+#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resources.*/
/* Extra flag about HWREna register. */
#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 66b7953..a23c4ed 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -53,6 +53,7 @@
#define ASE_MDMX 0x0000000400000000ULL
#define ASE_DSP 0x0000000800000000ULL
#define ASE_DSPR2 0x0000001000000000ULL
+#define ASE_DSPR3 0x0000002000000000ULL
#define ASE_MT 0x0000004000000000ULL
#define ASE_SMARTMIPS 0x0000008000000000ULL
#define ASE_MICROMIPS 0x0000010000000000ULL
--
2.7.4
- [Qemu-devel] [PULL 06/27] linux-user: Add infrastructure for handling MIPS-specific prctl(), (continued)
- [Qemu-devel] [PULL 06/27] linux-user: Add infrastructure for handling MIPS-specific prctl(), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 11/27] target/mips: Add organizational chart of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 25/27] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 17/27] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 16/27] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 22/27] target/mips: Add CP0 PWCtl register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 26/27] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 12/27] target/mips: Add opcode values of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 18/27] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 15/27] target/mips: Add bit definitions for DSP R3 ASE,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 21/27] target/mips: Add CP0 PWSize register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 20/27] target/mips: Add CP0 PWField register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 23/27] target/mips: Add reset state for PWSize and PWField registers, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 02/27] elf: Fix PT_MIPS_XXX constants, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 19/27] target/mips: Add CP0 PWBase register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 24/27] target/mips: Implement hardware page table walker for MIPS32, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 03/27] elf: Add MIPS_ABI_FP_XXX constants, Aleksandar Markovic, 2018/10/17
- Re: [Qemu-devel] [PULL 00/27]MIPS pull request for October 2018 - part 1, Peter Maydell, 2018/10/18