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[Qemu-devel] [PULL v2 19/28] target/mips: Add CP0 Config2 to DisasContex
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 19/28] target/mips: Add CP0 Config2 to DisasContext |
Date: |
Thu, 18 Oct 2018 20:47:44 +0200 |
From: Stefan Markovic <address@hidden>
Add field corresponding to CP0 Config2 to DisasContext. This is
needed for availability control via Config2 bits.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1f10f48..e26d54a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1988,6 +1988,7 @@ typedef struct DisasContext {
uint32_t opcode;
uint64_t insn_flags;
int32_t CP0_Config1;
+ int32_t CP0_Config2;
int32_t CP0_Config3;
int32_t CP0_Config5;
/* Routine used to access memory */
@@ -25835,6 +25836,7 @@ static void mips_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->saved_pc = -1;
ctx->insn_flags = env->insn_flags;
ctx->CP0_Config1 = env->CP0_Config1;
+ ctx->CP0_Config2 = env->CP0_Config2;
ctx->CP0_Config3 = env->CP0_Config3;
ctx->CP0_Config5 = env->CP0_Config5;
ctx->btarget = 0;
--
2.7.4
- [Qemu-devel] [PULL v2 16/28] target/mips: Add bit definitions for DSP R3 ASE, (continued)
- [Qemu-devel] [PULL v2 16/28] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 09/28] target/mips: Add a comment before each CP0 register section in cpu.h, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 13/28] target/mips: Add opcode values of MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 08/28] target/mips: Add a comment with an overview of CP0 registers, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 20/28] target/mips: Add CP0 PWBase register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 15/28] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 17/28] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 07/28] linux-user: Add infrastructure for handling MIPS-specific prctl(), Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 22/28] target/mips: Add CP0 PWSize register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 21/28] target/mips: Add CP0 PWField register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 19/28] target/mips: Add CP0 Config2 to DisasContext,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 24/28] target/mips: Add reset state for PWSize and PWField registers, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 27/28] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 14/28] target/mips: Increase 'supported ISAs/ASEs' flag holder size, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 10/28] target/mips: Add basic description of MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 12/28] target/mips: Add organizational chart of MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 23/28] target/mips: Add CP0 PWCtl register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 18/28] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 28/28] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 26/28] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>, Aleksandar Markovic, 2018/10/18