Re: [Qemu-devel] [PULL v2 14/28] target/mips: Increase 'supported ISAs/ASEs' flag holder size

[Philippe Mathieu-Daudé]

Hi Aleksandar,

On Thu, Oct 18, 2018 at 9:20 PM Aleksandar Markovic
<address@hidden> wrote:
>
> From: Philippe Mathieu-Daudé <address@hidden>
>
> Increase the size of insn_flags holder size to 64 bits. This is
> needed for future extensions since existing bits are almost all used.
>

Why did you remove my S-o-b tag...?

> Reviewed-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> ---
>  target/mips/cpu.h       | 2 +-
>  target/mips/internal.h  | 2 +-
>  target/mips/translate.c | 6 +++---
>  3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 37703ea..3b3509c 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -811,7 +811,7 @@ struct CPUMIPSState {
>      int CCRes; /* Cycle count resolution/divisor */
>      uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
>      uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
> -    int insn_flags; /* Supported instruction set */
> +    uint64_t insn_flags; /* Supported instruction set */
>
>      /* Fields up to this point are cleared by a CPU reset */
>      struct {} end_reset_fields;
> diff --git a/target/mips/internal.h b/target/mips/internal.h
> index e41051f..bfe83ee 100644
> --- a/target/mips/internal.h
> +++ b/target/mips/internal.h
> @@ -59,7 +59,7 @@ struct mips_def_t {
>      int32_t CP0_PageGrain_rw_bitmask;
>      int32_t CP0_PageGrain;
>      target_ulong CP0_EBaseWG_rw_bitmask;
> -    int insn_flags;
> +    uint64_t insn_flags;
>      enum mips_mmu_types mmu_type;
>  };
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index a309df7..c91c541 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1986,7 +1986,7 @@ typedef struct DisasContext {
>      target_ulong saved_pc;
>      target_ulong page_start;
>      uint32_t opcode;
> -    int insn_flags;
> +    uint64_t insn_flags;
>      int32_t CP0_Config1;
>      int32_t CP0_Config3;
>      int32_t CP0_Config5;
> @@ -2409,7 +2409,7 @@ static inline void check_dspr2(DisasContext *ctx)
>
>  /* This code generates a "reserved instruction" exception if the
>     CPU does not support the instruction set corresponding to flags. */
> -static inline void check_insn(DisasContext *ctx, int flags)
> +static inline void check_insn(DisasContext *ctx, uint64_t flags)
>  {
>      if (unlikely(!(ctx->insn_flags & flags))) {
>          generate_exception_end(ctx, EXCP_RI);
> @@ -2419,7 +2419,7 @@ static inline void check_insn(DisasContext *ctx, int 
> flags)
>  /* This code generates a "reserved instruction" exception if the
>     CPU has corresponding flag set which indicates that the instruction
>     has been removed. */
> -static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
> +static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
>  {
>      if (unlikely(ctx->insn_flags & flags)) {
>          generate_exception_end(ctx, EXCP_RI);
> --
> 2.7.4
>
>