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[Qemu-devel] [PATCH v5 02/14] target/mips: Define a bit for MXU in insn_
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v5 02/14] target/mips: Define a bit for MXU in insn_flags |
Date: |
Fri, 19 Oct 2018 18:33:36 +0200 |
From: Craig Janeczek <address@hidden>
Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/mips-defs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 71ea4ef..4c624a4 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -67,6 +67,7 @@
/*
* bits 56-63: vendor-specific ASEs
*/
+#define ASE_MXU 0x0100000000000000ULL
/* MIPS CPU defines. */
#define CPU_MIPS1 (ISA_MIPS1)
--
2.7.4
- [Qemu-devel] [PATCH v5 00/14] Add limited MXU instruction support, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 01/14] target/mips: Introduce MXU registers, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 02/14] target/mips: Define a bit for MXU in insn_flags,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v5 03/14] target/mips: Add and integrate MXU decoding engine placeholder, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 04/14] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 05/14] target/mips: Add bit encoding for MXU add/subtract patterns 'aptn2', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 08/14] target/mips: Add emulation of non-MXU MULL within MXU decoding engine, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 14/14] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 07/14] target/mips: Add bit encoding for MXU operand getting patterns 'optn3', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 06/14] target/mips: Add bit encoding for MXU operand getting patterns 'optn2', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 10/14] target/mips: Add emulation of MXU instruction S8LDD, Aleksandar Markovic, 2018/10/19