Re: [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree

[Richard Henderson]

On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> v1 -> v2:
>     - Stack allocate arg_c_* structs
>     - ex_rvc_register returns int
>     - special case of trans_c_addi4spn() returns false
...
> +static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a,
> +        uint16_t insn)
> +{
> +    if (a->nzuimm == 0) {
> +        /* Reserved in ISA */
> +        gen_exception_illegal(ctx);
> +        return true;
> +    }

That doesn't seem to have actually happened.

But otherwise,
Reviewed-by: Richard Henderson <address@hidden>

r~