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Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MS
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions |
Date: |
Wed, 3 Apr 2019 14:53:46 +0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 |
On 4/3/19 5:28 AM, Aleksandar Markovic wrote:
>> + tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
>> + tcg_gen_deposit_i64(msa_wr_d[wd * 2], t1, msa_wr_d[ws * 2], 32, 32);
>> +
>> + tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
>> + tcg_gen_deposit_i64(msa_wr_d[wd * 2 + 1], t1, msa_wr_d[ws * 2 + 1], 32,
>> 32);
>> +
>> + tcg_temp_free_i64(t1);
>> +}
>> +
>
> This can be further optimized this way: (doublecheck the accuracy, writing
> from
> home)
>
> gen_ilvev_w(CPUMIPSState *env, uint32_t wd,
> uint32_t ws, uint32_t wt)
> {
> tcg_gen_shli_i64(msa_wr_d[wd * 2], msa_wr_d[ws * 2], 32);
> tcg_gen_deposit_i64(msa_wr_d[wd * 2], t1, msa_wr_d[wt * 2], 0, 32);
>
No, the shift can be performed by the deposit.
See my other reply in this thread.
r~
- Re: [Qemu-devel] [PATCH v5 1/2] target/mips: Optimize ILVOD.<B|H|W|D> MSA instructions, (continued)
- Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions, Aleksandar Markovic, 2019/04/02
- Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions, Aleksandar Markovic, 2019/04/02
- Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions,
Richard Henderson <=
- Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions, Aleksandar Markovic, 2019/04/02
- Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions, Richard Henderson, 2019/04/03
- Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions, Aleksandar Markovic, 2019/04/03
Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions, Richard Henderson, 2019/04/03