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[Qemu-devel] [PULL 10/42] target/arm: Clear CONTROL_S.SFPA in SG insn if
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/42] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present |
Date: |
Mon, 29 Apr 2019 17:59:58 +0100 |
If the floating point extension is present, then the SG instruction
must clear the CONTROL_S.SFPA bit. Implement this.
(On a no-FPU system the bit will always be zero, so we don't need
to make the clearing of the bit conditional on ARM_FEATURE_VFP.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c3d5fe09cdc..45a9d92e505 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8804,6 +8804,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
", executing it\n", env->regs[15]);
env->regs[14] &= ~1;
+ env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
switch_v7m_security_state(env, true);
xpsr_write(env, 0, XPSR_IT);
env->regs[15] += 4;
--
2.20.1
- [Qemu-devel] [PULL 09/42] target/arm: Decode FP instructions for M profile, (continued)
- [Qemu-devel] [PULL 09/42] target/arm: Decode FP instructions for M profile, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 21/42] target/arm: Set FPCCR.S when executing M-profile floating point insns, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 08/42] target/arm: Honour M-profile FP enable bits, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 22/42] target/arm: Activate M-profile floating point context when FPCCR.ASPEN is set, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 24/42] target/arm: New function armv7m_nvic_set_pending_lazyfp(), Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 30/42] hw/dma: Compile the bcm2835_dma device as common object, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 32/42] hw/arm/nseries: Use TYPE_TMP105 instead of hardcoded string, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 04/42] target/arm: Make sure M-profile FPSCR RES0 bits are not settable, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 16/42] target/arm: Clean excReturn bits when tail chaining, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 28/42] target/arm: Implement VLLDM for v7M CPUs with an FPU, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 10/42] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present,
Peter Maydell <=
- [Qemu-devel] [PULL 41/42] hw/net/lan9118: Export TYPE_LAN9118 and use it instead of hardcoded string, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 12/42] target/arm/helper: don't return early for STKOF faults during stacking, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 27/42] target/arm: Implement VLSTM for v7M CPUs with an FPU, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 34/42] hw/devices: Move TC6393XB declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 20/42] target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 11/42] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 38/42] hw/devices: Move TI touchscreen declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 19/42] target/arm: Move NS TBFLAG from bit 19 to bit 6, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 39/42] hw/devices: Move LAN9118 declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 35/42] hw/devices: Move Blizzard declarations into a new header, Peter Maydell, 2019/04/29